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e683fa28c8
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Add power of two divider
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2025-11-19 15:50:34 -08:00 |
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ae5dcf1a4d
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Add BD to pwm_controller source list
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2025-11-19 15:48:08 -08:00 |
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5094eba511
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Remove AXI constraints
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2025-11-19 15:47:59 -08:00 |
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904b083688
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Add ZYNQ and AXI peripherals to BD
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2025-11-19 15:47:48 -08:00 |
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b33383ce5f
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Add pwm_controller block design
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2025-11-19 15:38:36 -08:00 |
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9f17c3f16f
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Update BD directory in .gitignore
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2025-11-19 15:38:26 -08:00 |
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a58148a92e
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Add RGB PWM AXI ip configuration
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2025-11-19 15:31:47 -08:00 |
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a2c0c9a972
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Add PWM axi to list
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2025-11-19 15:31:39 -08:00 |
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89fc1846d5
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Add RGB PWM AXI interface hdl
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2025-11-19 15:31:04 -08:00 |
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67bcca2aca
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Remove PWM block top testbench
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2025-11-19 15:04:37 -08:00 |
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b32ab40b0f
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Add PWM core testbench sim list
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2025-11-19 14:59:48 -08:00 |
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64f63e41b7
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Fix PWM core off by one error, and missing posedge(rst)
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2025-11-19 14:58:31 -08:00 |
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002d2c0c06
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Implement PWM core testbench
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2025-11-19 14:57:40 -08:00 |
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a352ed794c
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Add PWM core to project list
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2025-11-19 13:33:43 -08:00 |
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2695b69b21
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Add PWM core testbench module
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2025-11-19 13:24:13 -08:00 |
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6418f366b3
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Implement PWM core
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2025-11-19 13:22:29 -08:00 |
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7c2de42e2c
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Add pwm_core module
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2025-11-19 13:12:24 -08:00 |
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9d02715cb9
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Add UserIP directory to pwm_controller config
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2025-11-19 13:11:21 -08:00 |
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5421c7ccc9
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Modify package IP to delete temp project when finished
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2025-11-11 00:09:33 -08:00 |
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53aee5878e
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Remove frequency from ip configuration
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2025-11-11 00:08:48 -08:00 |
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cff5b413e7
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Rename memory map name to be more descriptive
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2025-11-11 00:08:35 -08:00 |
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ca6826d53d
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Don't load customization parameters from ip.conf, keep auto
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2025-11-11 00:07:05 -08:00 |
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cf43ac49d3
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Implement parsing memory map from ip.conf
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2025-11-11 00:06:17 -08:00 |
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49723910d8
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Fix DictValueOr default value returning "default" string
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2025-11-10 23:59:19 -08:00 |
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e42d640083
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Refactor IP parameter and port mapping into separate proc
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2025-11-10 23:14:37 -08:00 |
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51f3102fae
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Implement port mappings reading from ip.conf
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2025-11-10 22:49:42 -08:00 |
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68c9947d1a
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Fix IP interface not being set correctly
Need to set both bus abstraction and type, and they don't have the same
values
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2025-11-10 22:48:55 -08:00 |
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712206a524
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Rename MAP to PORT in ip.conf
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2025-11-10 22:48:14 -08:00 |
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913af7a46a
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Partially implement manual IP configuration, user parameter config
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2025-11-10 20:43:29 -08:00 |
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600eebbd11
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Change IP packaging configuration to use manual clk config
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2025-11-10 20:42:47 -08:00 |
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a6e86c8f3c
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Implement interface inferring
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2025-11-10 19:50:08 -08:00 |
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c2e6cec4e7
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Add AXI interfaces to led_controller IP packaging
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2025-11-10 19:49:45 -08:00 |
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46c000b94a
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Package IP and clear settings in package_ip.tcl
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2025-11-10 18:51:30 -08:00 |
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bdc55177cd
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Add script for packaging IP from project
Currently just reads the IP configuration
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2025-11-10 14:13:31 -08:00 |
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c242ff9445
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Add IP package configuration file to led_controller
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2025-11-10 14:11:35 -08:00 |
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8524f3908f
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Add led_controller Hog configuration
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2025-11-09 22:18:01 -08:00 |
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ee3c5dca87
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Add LED controller AXI controller for testing
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2025-11-09 22:15:56 -08:00 |
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50853a7762
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Add pwm_block project
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2025-11-09 20:52:31 -08:00 |
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ee-324
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d6cfc64b86
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Initial commit
v0.0.1
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2025-11-10 04:13:57 +00:00 |
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