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v0.0.1

Mono Color

• 1f1fe1dff0 Fix missing PWM clock wire trunk Madeline Busig 2025-12-03 02:17:57 -08:00
• 8a7ed7a61b Update RGB PWM IP source list Madeline Busig 2025-12-03 01:37:26 -08:00
• 631f46f339 Modify RGB PWM IP to use enable pulser instead of clock divider Madeline Busig 2025-12-03 01:36:41 -08:00
• 8ffe9271f2 Modify hardware implemented PWM controller to use enable pulser Madeline Busig 2025-12-03 00:07:02 -08:00
• 26eb01a9e8 Remove redundant clk_out from enable pulser Madeline Busig 2025-12-03 00:04:40 -08:00
• 6b441b12ae Add clock enable input to pwm_core Madeline Busig 2025-12-03 00:02:34 -08:00
• 31730fba46 Add clock enable pulser with testbench Madeline Busig 2025-12-02 23:56:01 -08:00
• 067e4c1f6a Fix incorrect oen pin in HW PWM controller Madeline Busig 2025-12-02 21:44:53 -08:00
• 941cbdf2dc Update HW PWM controller src list Madeline Busig 2025-12-02 21:33:53 -08:00
• 1c532bdd95 Add HW PWM controller top module Madeline Busig 2025-12-02 21:33:38 -08:00
• 616166f69f Add project for HW implementation of PWM controller Madeline Busig 2025-12-02 21:19:16 -08:00
• d85f2cf5d8 Updtae block design Madeline Busig 2025-11-19 16:16:33 -08:00
• ee6c3d2e60 Fix typos Madeline Busig 2025-11-19 16:06:20 -08:00
• ca29b6c586 Update block diagram, make external Madeline Busig 2025-11-19 15:57:04 -08:00
• 72b06dbcb4 Add clock divider functionality to PWM AXI Madeline Busig 2025-11-19 15:52:56 -08:00
• e683fa28c8 Add power of two divider Madeline Busig 2025-11-19 15:50:34 -08:00
• ae5dcf1a4d Add BD to pwm_controller source list Madeline Busig 2025-11-19 15:48:08 -08:00
• 5094eba511 Remove AXI constraints Madeline Busig 2025-11-19 15:47:59 -08:00
• 904b083688 Add ZYNQ and AXI peripherals to BD Madeline Busig 2025-11-19 15:47:48 -08:00
• b33383ce5f Add pwm_controller block design Madeline Busig 2025-11-19 15:38:36 -08:00
• 9f17c3f16f Update BD directory in .gitignore Madeline Busig 2025-11-19 15:38:26 -08:00
• a58148a92e Add RGB PWM AXI ip configuration Madeline Busig 2025-11-19 15:31:47 -08:00
• a2c0c9a972 Add PWM axi to list Madeline Busig 2025-11-19 15:31:39 -08:00
• 89fc1846d5 Add RGB PWM AXI interface hdl Madeline Busig 2025-11-19 15:31:04 -08:00
• 67bcca2aca Remove PWM block top testbench Madeline Busig 2025-11-19 15:04:37 -08:00
• b32ab40b0f Add PWM core testbench sim list Madeline Busig 2025-11-19 14:59:48 -08:00
• 64f63e41b7 Fix PWM core off by one error, and missing posedge(rst) Madeline Busig 2025-11-19 14:58:31 -08:00
• 002d2c0c06 Implement PWM core testbench Madeline Busig 2025-11-19 14:57:40 -08:00
• a352ed794c Add PWM core to project list Madeline Busig 2025-11-19 13:33:43 -08:00
• 2695b69b21 Add PWM core testbench module Madeline Busig 2025-11-19 13:24:13 -08:00
• 6418f366b3 Implement PWM core Madeline Busig 2025-11-19 13:22:29 -08:00
• 7c2de42e2c Add pwm_core module Madeline Busig 2025-11-19 13:12:24 -08:00
• 9d02715cb9 Add UserIP directory to pwm_controller config Madeline Busig 2025-11-19 13:11:21 -08:00
• 5421c7ccc9 Modify package IP to delete temp project when finished Madeline Busig 2025-11-11 00:09:33 -08:00
• 53aee5878e Remove frequency from ip configuration Madeline Busig 2025-11-11 00:08:48 -08:00
• cff5b413e7 Rename memory map name to be more descriptive Madeline Busig 2025-11-11 00:08:35 -08:00
• ca6826d53d Don't load customization parameters from ip.conf, keep auto Madeline Busig 2025-11-11 00:07:05 -08:00
• cf43ac49d3 Implement parsing memory map from ip.conf Madeline Busig 2025-11-11 00:06:17 -08:00
• 49723910d8 Fix DictValueOr default value returning "default" string Madeline Busig 2025-11-10 23:59:19 -08:00
• e42d640083 Refactor IP parameter and port mapping into separate proc Madeline Busig 2025-11-10 23:14:37 -08:00
• 51f3102fae Implement port mappings reading from ip.conf Madeline Busig 2025-11-10 22:49:42 -08:00
• 68c9947d1a Fix IP interface not being set correctly Madeline Busig 2025-11-10 22:48:55 -08:00
• 712206a524 Rename MAP to PORT in ip.conf Madeline Busig 2025-11-10 22:48:14 -08:00
• 913af7a46a Partially implement manual IP configuration, user parameter config Madeline Busig 2025-11-10 20:43:29 -08:00
• 600eebbd11 Change IP packaging configuration to use manual clk config Madeline Busig 2025-11-10 20:42:47 -08:00
• a6e86c8f3c Implement interface inferring Madeline Busig 2025-11-10 19:50:08 -08:00
• c2e6cec4e7 Add AXI interfaces to led_controller IP packaging Madeline Busig 2025-11-10 19:49:45 -08:00
• 46c000b94a Package IP and clear settings in package_ip.tcl Madeline Busig 2025-11-10 18:51:30 -08:00
• bdc55177cd Add script for packaging IP from project Madeline Busig 2025-11-10 14:13:31 -08:00
• c242ff9445 Add IP package configuration file to led_controller Madeline Busig 2025-11-10 14:11:35 -08:00
• 8524f3908f Add led_controller Hog configuration Madeline Busig 2025-11-09 22:18:01 -08:00
• ee3c5dca87 Add LED controller AXI controller for testing Madeline Busig 2025-11-09 22:15:56 -08:00
• 50853a7762 Add pwm_block project Madeline Busig 2025-11-09 20:52:31 -08:00
• d6cfc64b86 Initial commit v0.0.1 ee-324 2025-11-10 04:13:57 +00:00