Add build files
This commit is contained in:
Madeline Busig
parent
a994c0a5fc
commit
14a69ac058
64
Makefile
Normal file
64
Makefile
Normal file
@ -0,0 +1,64 @@
|
||||
TOP := top
|
||||
CNSTRFILE := constraints.xdc
|
||||
PART := xc7z007sclg400-1
|
||||
|
||||
HW_SERVER := localhost:3121
|
||||
HW_TARGET := $(HW_SERVER)/xilinx_tcf/Xilinx/*
|
||||
HW_DEVICE := xc7z007s_1
|
||||
|
||||
SRCDIR := $(realpath src)
|
||||
DCPDIR := dcp
|
||||
BINDIR := bin
|
||||
TBDIR := $(realpath tb)
|
||||
DUMPDIR := dump
|
||||
TBBINDIR := $(BINDIR)/tb
|
||||
|
||||
SCRIPT_SYNTH := $(shell realpath tcl/synth.tcl)
|
||||
SCRIPT_IMPL := $(shell realpath tcl/impl.tcl)
|
||||
SCRIPT_GENBIT := $(shell realpath tcl/genbit.tcl)
|
||||
SCRIPT_PROGDEV := $(shell realpath tcl/prog_device.tcl)
|
||||
SCRIPT_RUNTB := $(shell realpath sh/runtb.sh)
|
||||
SCRIPT_TBLOGVCD := $(shell realpath tcl/tblogvcd.tcl)
|
||||
|
||||
VERILATORFLAGS := --cc -Wno-WIDTH -Wno-UNOPTFLAT --trace --trace-structs --binary -I$(SRCDIR) -I$(TBDIR)
|
||||
|
||||
default: all
|
||||
all : synth impl genbit
|
||||
|
||||
synth : $(DCPDIR)/default.synth.dcp
|
||||
impl : $(DCPDIR)/default.impl.dcp
|
||||
genbit : $(BINDIR)/default.bit
|
||||
prog_device : prog_device.default
|
||||
|
||||
clean :
|
||||
@if [ -d $(DCPDIR) ]; then rm -r $(DCPDIR); fi
|
||||
@if [ -d $(BINDIR) ]; then rm -r $(BINDIR); fi
|
||||
|
||||
### Synthesis/implementation/programming rules
|
||||
|
||||
$(DCPDIR)/%.synth.dcp : $(wildcard $(SRCDIR)/*.v)
|
||||
mkdir -p $(DCPDIR)
|
||||
vivado -nolog -nojournal -mode batch -source $(SCRIPT_SYNTH) -tclargs $@ $(PART) $(TOP) $^
|
||||
|
||||
$(DCPDIR)/%.impl.dcp : $(DCPDIR)/%.synth.dcp
|
||||
vivado -nolog -nojournal -mode batch -source $(SCRIPT_IMPL) -tclargs $@ $< $(CNSTRFILE)
|
||||
|
||||
$(BINDIR)/%.bit : $(DCPDIR)/%.impl.dcp
|
||||
mkdir -p $(BINDIR)
|
||||
vivado -nolog -nojournal -mode batch -source $(SCRIPT_GENBIT) -tclargs $@ $<
|
||||
|
||||
prog_device.% : $(BINDIR)/%.bit
|
||||
vivado -nolog -nojournal -mode batch -source $(SCRIPT_PROGDEV) -tclargs $< $(HW_SERVER) $(HW_TARGET) $(HW_DEVICE)
|
||||
|
||||
### Testbench rules
|
||||
|
||||
.NOTINTERMEDIATE : $(TBBINDIR)/%/dump.vcd
|
||||
$(TBBINDIR)/%/dump.vcd : $(wildcard $(TBDIR)/*.v) $(wildcard $(SRCDIR)/*.v)
|
||||
mkdir -p $(TBBINDIR)/$*
|
||||
cd $(TBBINDIR)/$* && $(SCRIPT_RUNTB) $(SCRIPT_TBLOGVCD) $* $^
|
||||
|
||||
viewdump.% : $(TBBINDIR)/%/dump.vcd
|
||||
nohup gtkwave $< &> /dev/null &
|
||||
|
||||
runtb.% : $(TBBINDIR)/%/dump.vcd
|
||||
|
||||
132
constraints.xdc
Normal file
132
constraints.xdc
Normal file
@ -0,0 +1,132 @@
|
||||
## Master .xdc for the Blackboard
|
||||
|
||||
##Clock
|
||||
set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }];
|
||||
|
||||
#Individual LEDS
|
||||
set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L14P_T2_SRCC_34 Schematic=LD0
|
||||
set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L14N_T2_SRCC_34 Schematic=LD1
|
||||
set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_34 Schematic=LD2
|
||||
set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_34 Schematic=LD3
|
||||
set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L3P_T0_DWS_PUDC_B_34 Schematic=LD4
|
||||
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_25_34 Schematic=LD5
|
||||
set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L16N_T2_34 Schematic=LD6
|
||||
set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L17N_T2_34 Schematic=LD7
|
||||
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16P_T2_34 Schematic=LD8
|
||||
set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L22N_T3_34 Schematic=LD9
|
||||
|
||||
#RGB_LEDS
|
||||
set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_A[0] }]; #IO_L22P_T3_34 Schematic=LD10_R
|
||||
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_A[1] }]; #IO_L18N_T2_34 Schematic=LD10_G
|
||||
set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_A[2] }]; #IO_L17P_T2_34 Schematic=LD10_B
|
||||
|
||||
set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_B[0] }]; #IO_L8N_T1_34 Schematic=LD11_R
|
||||
set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_B[1] }]; #IO_L7P_T1_34 Schematic=LD11_G
|
||||
set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_B[2] }]; #IO_L7N_T1_34 Schematic=LD11_B
|
||||
|
||||
#Switches
|
||||
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_34 Schematic=SW0
|
||||
set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L15N_T2_DQS_34 Schematic=SW1
|
||||
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L19P_T3_34 Schematic=SW2
|
||||
set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L21N_T3_DQS_AD14N_35 Schematic=SW3
|
||||
set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L6N_T0_VREF_34 Schematic=SW4
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L6P_T0_34 Schematic=SW5
|
||||
set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L22N_T3_AD7N_35 Schematic=SW6
|
||||
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L23N_T3_35 Schematic=SW7
|
||||
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { sw[8] }]; #IO_L10P_T1_34 Sch=VGA_R4_CON
|
||||
set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { sw[9] }]; #IO_L10N_T1_34 Sch=VGA_R5_CON
|
||||
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L18P_T2_34 Sch=VGA_R6_CON
|
||||
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R7_CON
|
||||
|
||||
#Push Buttons
|
||||
set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L8P_T1_34 Schematic=BTN0
|
||||
set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_34 Schematic=BTN1
|
||||
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L24P_T3_34 Schematic=BTN2
|
||||
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L23P_T3_35 Schematic=BTN3
|
||||
|
||||
#Seven Segmen Display Anodes
|
||||
set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { seg_an[0] }]; #IO_L10P_T1_AD11P_35 Schematic=SSEG_AN0
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { seg_an[1] }]; #IO_L13N_T2_MRCC_35 Schematic=SSEG_AN1
|
||||
set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { seg_an[2] }]; #IO_L8N_T1_AD10N_35 Schematic=SSEG_AN2
|
||||
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { seg_an[3] }]; #IO_L11P_T1_SRCC_35 Schematic=SSEG_AN3
|
||||
|
||||
#Seven Segmen Display Cathodes
|
||||
set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[0] }]; #IO_L20P_T3_AD6P_35 Schematic=SSEG_CA
|
||||
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[1] }]; #IO_L19P_T3_35 Schematic=SSEG_CB
|
||||
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Schematic=SSEG_CC
|
||||
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[3] }]; #IO_25_35 Schematic=SSEG_CD
|
||||
set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[4] }]; #IO_L8P_T1_AD10P_35 Schematic=SSEG_CE
|
||||
set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[5] }]; #IO_L24N_T3_AD15N_35 Schematic=SSEG_CF
|
||||
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[6] }]; #IO_L8P_T1_AD10P_35 Schematic=SSEG_CG
|
||||
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[7] }]; #IO_L12N_T1_MRCC_35 Schematic=SSEG_DP
|
||||
|
||||
##Accelerometer/Gyroscope/Magnetometer
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { GYRO_SCL }]; #IO_L17N_T2_AD5N_35 Schematic=GYRO_SCL
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { GYRO_SDA }]; #IO_L10N_T1_AD11N_35 Schematic=GYRO_SDA
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { GYRO_SDO_A/G }]; #IO_L17P_T2_AD5P_35 Schematic=GYRO_SDO_A/G
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { GYRO_SDO_M }]; #IO_L11N_T1_SRCC_35 Schematic=GYRO_SDO_M
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { GYRO_CS_A/G }]; #IO_L12P_T1_MRCC_35 Schematic=GYRO_CS_A/G
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { GYRO_CS_M }]; #IO_L24P_T3_AD15P_35 Schematic=GYRO_CS_M
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { DEN_A_G }]; #IO_L20N_T3_AD6N_35 Schematic=GYRO_DEN_A/G
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { DRDY_M }]; #IO_L9N_T1_DQS_AD3N_35 Schematic=GYRO_DRDY_M
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { INT_A_G }]; #IO_L7N_T1_AD2N_35 Schematic=GYRO_INT_A/G
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { INT_M }]; #IO_L9P_T1_DQS_AD3P_35 Schematic=GYRO_INT_M
|
||||
|
||||
##MIC
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { M_clk }]; #IO_L21P_T3_DQS_AD14P_35 Schematic=M_CLK
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { M_data }]; #IO_L22P_T3_AD7P_35 Schematic=M_DATA
|
||||
|
||||
##Speaker
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { headphone }]; #IO_L16N_T2_35 Schematic=AUDIO
|
||||
|
||||
|
||||
##HDMI Signals
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports hdmi_clk_n]; #IO_L12N_T1_MRCC_34 Sch=HDMI_TX_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports hdmi_clk_p]; #IO_L12P_T1_MRCC_34 Sch=HDMI_TX_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_n[0]]; #IO_L21N_T3_DQS_34 Sch=HDMI_TX0_N
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_p[0]]; #IO_L21P_T3_DQS_34 Sch=HDMI_TX0_P
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_n[1]]; #IO_L23N_T3_34 Sch=HDMI_TX1_N
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_p[1]]; #IO_L23P_T3_34 Sch=HDMI_TX1_P
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_n[2]]; #IO_L13N_T2_MRCC_34 Sch=HDMI_TX2_N
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_p[2]]; #IO_L13P_T2_MRCC_34 Sch=HDMI_TX2_P
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L9N_T1_DQS_34 Sch=HDMI_TX_CEC
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L24N_T3_34 Sch=HDMI_TX_HPD
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L20P_T3_34 Sch=HDMI_TX_SCL
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L20N_T3_34 Sch=HDMI_TX_SDA
|
||||
|
||||
##PmodA
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JA1_P }]; #IO_L6P_T0_35 Sch=JA1_P
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { JA1_N }]; #IO_L6N_T0_VREF_35 Sch=JA1_N
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { JA2_P }]; #IO_L18P_T2_AD13P_35 Sch=JA2_P
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { JA2_N }]; #IO_L18N_T2_AD13N_35 Sch=JA2_N
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA3_P }]; #IO_L5P_T0_AD9P_35 Sch=JA3_P
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { JA3_N }]; #IO_L5N_T0_AD9N_35 Sch=JA3_N
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA4_P }]; #IO_L3P_T0_DQS_AD1P_35 Sch=JA4_P
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA4_N }]; #IO_L3N_T0_DQS_AD1N_35 Sch=JA4_N
|
||||
|
||||
##PmodB
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { JB1_P }]; #IO_L4P_T0_35 Sch=JB1_P
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { JB1_N }]; #IO_L4N_T0_35 Sch=JB1_N
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { JB2_P }]; #IO_L15P_T2_DQS_AD12P_35 Sch=JB2_P
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { JB2_N }]; #IO_L15N_T2_DQS_AD12N_35 Sch=JB2_N
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { JB3_P }]; #IO_L1P_T0_AD0P_35 Sch=JB3_P
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { JB3_N }]; #IO_L1N_T0_AD0N_35 Sch=JB3_N
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { JB4_P }]; #IO_L2P_T0_AD8P_35 Sch=JB4_P
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { JB4_N }]; #IO_L2N_T0_AD8N_35 Sch=JB4_N
|
||||
|
||||
##PmodC
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { JC1 }]; #IO_L10P_T1_34 Sch=JC1
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { JC2 }]; #IO_L10N_T1_34 Sch=JC2
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { JC3 }]; #IO_L18P_T2_34 Sch=JC3
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { JC4 }]; #IO_LP9_T1_DQS_34 Sch=JC4
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { JC7 }]; #IO_L7P_T1_AD2P_35 Sch=JC7
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { JC8 }]; #IO_0_35 Sch=JC8
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JC9 }]; #IO_L16P_T2_35 Sch=JC9
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { JC10 }]; #IO_L19N_T3_VREF_35 Sch=JC10
|
||||
|
||||
#Servos
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports servo[0]]; #IO_L16P_T2_35 Sch=SERVO1
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports servo[1]]; #IO_L19N_T3_VREF_35 Sch=SERVO2
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports servo[2]]; #IO_0_35 Sch=SERVO3
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports servo[3]]; #IO_L7P_T1_AD2P_35 Sch=SERVO4
|
||||
15
sh/runtb.sh
Executable file
15
sh/runtb.sh
Executable file
@ -0,0 +1,15 @@
|
||||
#!/usr/bin/bash
|
||||
|
||||
TBLOGVCD_TCL=$1
|
||||
TBMODULE=$2
|
||||
SOURCES=${@:3}
|
||||
|
||||
echo "Preparing testbench module $TBMODULE"
|
||||
echo "Reading verilog sources: $SOURCES"
|
||||
|
||||
xvlog $SOURCES
|
||||
xelab -debug typical $TBMODULE
|
||||
|
||||
echo "Running simulation and generating dump.vcd"
|
||||
xsim $TBMODULE --tclbatch $TBLOGVCD_TCL
|
||||
|
||||
18
tcl/genbit.tcl
Normal file
18
tcl/genbit.tcl
Normal file
@ -0,0 +1,18 @@
|
||||
if { $argc < 2 } {
|
||||
error "Usage: vivado -mode batch -source impl.tcl -tclargs BITFILE IMPL_CDP"
|
||||
} else {
|
||||
puts "All OK"
|
||||
}
|
||||
|
||||
variable BITFILE [lindex $argv 0]
|
||||
variable IMPL_DCP [lindex $argv 1]
|
||||
|
||||
puts "Using implementation DCP $IMPL_DCP"
|
||||
puts "Generating bit file $BITFILE"
|
||||
|
||||
puts "Opening checkpoint"
|
||||
open_checkpoint "$IMPL_DCP"
|
||||
|
||||
puts "Generating bitstream"
|
||||
write_bitstream -force "$BITFILE"
|
||||
|
||||
37
tcl/impl.tcl
Normal file
37
tcl/impl.tcl
Normal file
@ -0,0 +1,37 @@
|
||||
if { $argc < 3 } {
|
||||
error "Usage: vivado -mode batch -source impl.tcl -tclargs DCP SYNTH_DCP CONSTR"
|
||||
} else {
|
||||
puts "All OK"
|
||||
}
|
||||
|
||||
variable DCP [lindex $argv 0]
|
||||
variable SYNTH_DCP [lindex $argv 1]
|
||||
variable CONSTR [lindex $argv 2]
|
||||
|
||||
puts "Using syntheized DCP $SYNTH_DCP"
|
||||
puts "Using constraints file $CONSTR"
|
||||
puts "Synthesizing to DCP $DCP"
|
||||
|
||||
puts "Opening checkpoint"
|
||||
open_checkpoint "$SYNTH_DCP"
|
||||
|
||||
puts "Reading XDC"
|
||||
read_xdc $CONSTR
|
||||
|
||||
# You will get DRC errors without the next two lines
|
||||
# when generating a bitstream (Why??, true??)
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
|
||||
puts "Optimizing design"
|
||||
opt_design
|
||||
|
||||
puts "Placing design"
|
||||
place_design
|
||||
|
||||
puts "Routing design"
|
||||
route_design
|
||||
|
||||
puts "Writing design checkpoint"
|
||||
write_checkpoint -force "$DCP"
|
||||
|
||||
29
tcl/prog_device.tcl
Normal file
29
tcl/prog_device.tcl
Normal file
@ -0,0 +1,29 @@
|
||||
if { $argc < 4 } {
|
||||
error "Usage: vivado -mode batch -source synth.tcl -tclargs BITFILE HW_SERVER HW_TARGET HW_DEVICE"
|
||||
} else {
|
||||
puts "All OK"
|
||||
}
|
||||
|
||||
variable BITFILE [lindex $argv 0]
|
||||
variable HW_SERVER [lindex $argv 1]
|
||||
variable HW_TARGET [lindex $argv 2]
|
||||
variable HW_DEVICE [lindex $argv 3]
|
||||
|
||||
puts "Writing $BITFILE to $HW_DEVICE at $HW_TARGET"
|
||||
|
||||
puts "Opening hardware target"
|
||||
|
||||
open_hw_manager
|
||||
connect_hw_server -url $HW_SERVER
|
||||
current_hw_target [get_hw_targets $HW_TARGET]
|
||||
open_hw_target
|
||||
|
||||
puts "Setting device"
|
||||
current_hw_device $HW_DEVICE
|
||||
refresh_hw_device [current_hw_device]
|
||||
|
||||
puts "Programming device"
|
||||
set_property PROGRAM.file "$BITFILE" [current_hw_device]
|
||||
program_hw_devices [current_hw_device]
|
||||
refresh_hw_device [current_hw_device]
|
||||
|
||||
6
tcl/run.tcl
Normal file
6
tcl/run.tcl
Normal file
@ -0,0 +1,6 @@
|
||||
namespace eval run {
|
||||
proc synth {top {dcp ""}} {
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
31
tcl/synth.tcl
Normal file
31
tcl/synth.tcl
Normal file
@ -0,0 +1,31 @@
|
||||
if { $argc < 4 } {
|
||||
error "Usage: vivado -mode batch -source synth.tcl -tclargs DCP PART TOP SRCFILES"
|
||||
} else {
|
||||
puts "All OK"
|
||||
}
|
||||
|
||||
variable DCP [lindex $argv 0]
|
||||
variable PART [lindex $argv 1]
|
||||
variable TOP [lindex $argv 2]
|
||||
variable SRCFILES [lrange ${argv} 3 end]
|
||||
|
||||
puts "Synthesizing to DCP $DCP"
|
||||
puts "Using part $PART"
|
||||
puts "Using top module $TOP"
|
||||
puts "Synthesizing sources $SRCFILES"
|
||||
|
||||
if {[llength $SRCFILES] == 0} {
|
||||
error "No Verilog sources"
|
||||
}
|
||||
|
||||
link_design -part $PART
|
||||
|
||||
puts "Reading Verilog sources"
|
||||
read_verilog $SRCFILES
|
||||
|
||||
puts "Synthesizing design"
|
||||
synth_design -top $TOP -flatten_hierarchy full
|
||||
|
||||
puts "Writing Design Checkpoint"
|
||||
write_checkpoint -force "$DCP"
|
||||
|
||||
6
tcl/tblogvcd.tcl
Normal file
6
tcl/tblogvcd.tcl
Normal file
@ -0,0 +1,6 @@
|
||||
open_vcd dump.vcd
|
||||
log_vcd *
|
||||
run -all
|
||||
close_vcd
|
||||
quit
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user