32 lines
670 B
Tcl
32 lines
670 B
Tcl
if { $argc < 4 } {
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error "Usage: vivado -mode batch -source synth.tcl -tclargs DCP PART TOP SRCFILES"
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} else {
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puts "All OK"
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}
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variable DCP [lindex $argv 0]
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variable PART [lindex $argv 1]
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variable TOP [lindex $argv 2]
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variable SRCFILES [lrange ${argv} 3 end]
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puts "Synthesizing to DCP $DCP"
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puts "Using part $PART"
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puts "Using top module $TOP"
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puts "Synthesizing sources $SRCFILES"
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if {[llength $SRCFILES] == 0} {
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error "No Verilog sources"
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}
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link_design -part $PART
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puts "Reading Verilog sources"
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read_verilog $SRCFILES
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puts "Synthesizing design"
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synth_design -top $TOP -flatten_hierarchy full
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puts "Writing Design Checkpoint"
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write_checkpoint -force "$DCP"
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