9 Commits

Author SHA1 Message Date
31730fba46 Add clock enable pulser with testbench
Clock divider implemented in RTL does not get implemented properly when
used inside IP block. Instead, this module will pulse an enable pin at
the same intervals, which will be used by other modules instead of a
separate clock.
2025-12-02 23:56:01 -08:00
ee6c3d2e60 Fix typos 2025-11-19 16:06:20 -08:00
72b06dbcb4 Add clock divider functionality to PWM AXI 2025-11-19 15:52:56 -08:00
e683fa28c8 Add power of two divider 2025-11-19 15:50:34 -08:00
89fc1846d5 Add RGB PWM AXI interface hdl 2025-11-19 15:31:04 -08:00
64f63e41b7 Fix PWM core off by one error, and missing posedge(rst) 2025-11-19 14:58:31 -08:00
6418f366b3 Implement PWM core 2025-11-19 13:22:29 -08:00
7c2de42e2c Add pwm_core module 2025-11-19 13:12:24 -08:00
50853a7762 Add pwm_block project 2025-11-09 20:52:31 -08:00