6 Commits

Author	SHA1	Message	Date
Madeline Busig	6b441b12ae	Add clock enable input to pwm_core	2025-12-03 00:02:34 -08:00
Madeline Busig	31730fba46	Add clock enable pulser with testbench ... Clock divider implemented in RTL does not get implemented properly when used inside IP block. Instead, this module will pulse an enable pin at the same intervals, which will be used by other modules instead of a separate clock.	2025-12-02 23:56:01 -08:00
Madeline Busig	67bcca2aca	Remove PWM block top testbench	2025-11-19 15:04:37 -08:00
Madeline Busig	002d2c0c06	Implement PWM core testbench	2025-11-19 14:57:40 -08:00
Madeline Busig	2695b69b21	Add PWM core testbench module	2025-11-19 13:24:13 -08:00
Madeline Busig	50853a7762	Add pwm_block project	2025-11-09 20:52:31 -08:00