12 Commits

Author	SHA1	Message	Date
Madeline Busig	ee6c3d2e60	Fix typos	2025-11-19 16:06:20 -08:00
Madeline Busig	72b06dbcb4	Add clock divider functionality to PWM AXI	2025-11-19 15:52:56 -08:00
Madeline Busig	e683fa28c8	Add power of two divider	2025-11-19 15:50:34 -08:00
Madeline Busig	5094eba511	Remove AXI constraints	2025-11-19 15:47:59 -08:00
Madeline Busig	89fc1846d5	Add RGB PWM AXI interface hdl	2025-11-19 15:31:04 -08:00
Madeline Busig	67bcca2aca	Remove PWM block top testbench	2025-11-19 15:04:37 -08:00
Madeline Busig	64f63e41b7	Fix PWM core off by one error, and missing posedge(rst)	2025-11-19 14:58:31 -08:00
Madeline Busig	002d2c0c06	Implement PWM core testbench	2025-11-19 14:57:40 -08:00
Madeline Busig	2695b69b21	Add PWM core testbench module	2025-11-19 13:24:13 -08:00
Madeline Busig	6418f366b3	Implement PWM core	2025-11-19 13:22:29 -08:00
Madeline Busig	7c2de42e2c	Add pwm_core module	2025-11-19 13:12:24 -08:00
Madeline Busig	50853a7762	Add pwm_block project	2025-11-09 20:52:31 -08:00