1f1fe1dff0
Fix missing PWM clock wire
2025-12-03 02:17:57 -08:00
631f46f339
Modify RGB PWM IP to use enable pulser instead of clock divider
2025-12-03 01:36:41 -08:00
26eb01a9e8
Remove redundant clk_out from enable pulser
...
Was just passing through
2025-12-03 00:04:40 -08:00
6b441b12ae
Add clock enable input to pwm_core
2025-12-03 00:02:34 -08:00
31730fba46
Add clock enable pulser with testbench
...
Clock divider implemented in RTL does not get implemented properly when
used inside IP block. Instead, this module will pulse an enable pin at
the same intervals, which will be used by other modules instead of a
separate clock.
2025-12-02 23:56:01 -08:00
ee6c3d2e60
Fix typos
2025-11-19 16:06:20 -08:00
72b06dbcb4
Add clock divider functionality to PWM AXI
2025-11-19 15:52:56 -08:00
e683fa28c8
Add power of two divider
2025-11-19 15:50:34 -08:00
5094eba511
Remove AXI constraints
2025-11-19 15:47:59 -08:00
89fc1846d5
Add RGB PWM AXI interface hdl
2025-11-19 15:31:04 -08:00
67bcca2aca
Remove PWM block top testbench
2025-11-19 15:04:37 -08:00
64f63e41b7
Fix PWM core off by one error, and missing posedge(rst)
2025-11-19 14:58:31 -08:00
002d2c0c06
Implement PWM core testbench
2025-11-19 14:57:40 -08:00
2695b69b21
Add PWM core testbench module
2025-11-19 13:24:13 -08:00
6418f366b3
Implement PWM core
2025-11-19 13:22:29 -08:00
7c2de42e2c
Add pwm_core module
2025-11-19 13:12:24 -08:00
50853a7762
Add pwm_block project
2025-11-09 20:52:31 -08:00
