8 Commits

Author	SHA1	Message	Date
Madeline Busig	8a7ed7a61b	Update RGB PWM IP source list	2025-12-03 01:37:26 -08:00
Madeline Busig	31730fba46	Add clock enable pulser with testbench ... Clock divider implemented in RTL does not get implemented properly when used inside IP block. Instead, this module will pulse an enable pin at the same intervals, which will be used by other modules instead of a separate clock.	2025-12-02 23:56:01 -08:00
Madeline Busig	72b06dbcb4	Add clock divider functionality to PWM AXI	2025-11-19 15:52:56 -08:00
Madeline Busig	a2c0c9a972	Add PWM axi to list	2025-11-19 15:31:39 -08:00
Madeline Busig	67bcca2aca	Remove PWM block top testbench	2025-11-19 15:04:37 -08:00
Madeline Busig	b32ab40b0f	Add PWM core testbench sim list	2025-11-19 14:59:48 -08:00
Madeline Busig	a352ed794c	Add PWM core to project list	2025-11-19 13:33:43 -08:00
Madeline Busig	50853a7762	Add pwm_block project	2025-11-09 20:52:31 -08:00