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Add clock divider functionality to PWM AXI

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This commit is contained in:
Madeline Busig 2025-11-19 15:52:56 -08:00
parent e683fa28c8
commit 72b06dbcb4
2 changed files with 11 additions and 1 deletions
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1
Top/pwm_block/list/pwm_block.src
View File

@ -1,4 +1,5 @@
pwm_block/src/rgb_pwm_block.v top=rgb_pwm_block
pwm_block/src/rgb_pwm_block_S_AXI.v
pwm_block/src/pwm_core.v
pwm_block/src/conf_div.v

11
pwm_block/src/rgb_pwm_block_S_AXI.v
View File

@ -410,9 +410,18 @@
wire [15:0] duty_B = slv_reg2[15:0];
wire [15:0] widow_width = slv_reg3[31:16];
wire [15:0] pwm_clk_freq = slv_reg3[15:8];
wire [3:0] pwm_clk_mod = slv_reg3[11:8];
wire [15:0] pwm_oen = slv_reg3[0];
wire pwm_clk;
conf_div clk_div (
.clk_in(S_AXI_ACLK),
.rst(S_AXI_ARESETN),
.sel(pwm_clk_mod),
.clk_out(pwm_clk)
);
pwm_core core_R(
.clk(pwm_clk),
.rst(rst),