From 72b06dbcb4d8f02deb0ca4cfc22af69713fe6576 Mon Sep 17 00:00:00 2001 From: Madeline Busig Date: Wed, 19 Nov 2025 15:52:56 -0800 Subject: [PATCH] Add clock divider functionality to PWM AXI --- Top/pwm_block/list/pwm_block.src | 1 + pwm_block/src/rgb_pwm_block_S_AXI.v | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/Top/pwm_block/list/pwm_block.src b/Top/pwm_block/list/pwm_block.src index df9a99d..49588b3 100644 --- a/Top/pwm_block/list/pwm_block.src +++ b/Top/pwm_block/list/pwm_block.src @@ -1,4 +1,5 @@ pwm_block/src/rgb_pwm_block.v top=rgb_pwm_block pwm_block/src/rgb_pwm_block_S_AXI.v pwm_block/src/pwm_core.v +pwm_block/src/conf_div.v diff --git a/pwm_block/src/rgb_pwm_block_S_AXI.v b/pwm_block/src/rgb_pwm_block_S_AXI.v index 1323382..ac0fbd4 100644 --- a/pwm_block/src/rgb_pwm_block_S_AXI.v +++ b/pwm_block/src/rgb_pwm_block_S_AXI.v @@ -410,9 +410,18 @@ wire [15:0] duty_B = slv_reg2[15:0]; wire [15:0] widow_width = slv_reg3[31:16]; - wire [15:0] pwm_clk_freq = slv_reg3[15:8]; + wire [3:0] pwm_clk_mod = slv_reg3[11:8]; wire [15:0] pwm_oen = slv_reg3[0]; + wire pwm_clk; + + conf_div clk_div ( + .clk_in(S_AXI_ACLK), + .rst(S_AXI_ARESETN), + .sel(pwm_clk_mod), + .clk_out(pwm_clk) + ); + pwm_core core_R( .clk(pwm_clk), .rst(rst),