generated from maddiebusig/vivado-template-hog
Add clock divider functionality to PWM AXI
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@ -1,4 +1,5 @@
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pwm_block/src/rgb_pwm_block.v top=rgb_pwm_block
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pwm_block/src/rgb_pwm_block.v top=rgb_pwm_block
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pwm_block/src/rgb_pwm_block_S_AXI.v
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pwm_block/src/rgb_pwm_block_S_AXI.v
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pwm_block/src/pwm_core.v
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pwm_block/src/pwm_core.v
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pwm_block/src/conf_div.v
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@ -410,9 +410,18 @@
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wire [15:0] duty_B = slv_reg2[15:0];
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wire [15:0] duty_B = slv_reg2[15:0];
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wire [15:0] widow_width = slv_reg3[31:16];
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wire [15:0] widow_width = slv_reg3[31:16];
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wire [15:0] pwm_clk_freq = slv_reg3[15:8];
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wire [3:0] pwm_clk_mod = slv_reg3[11:8];
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wire [15:0] pwm_oen = slv_reg3[0];
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wire [15:0] pwm_oen = slv_reg3[0];
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wire pwm_clk;
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conf_div clk_div (
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.clk_in(S_AXI_ACLK),
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.rst(S_AXI_ARESETN),
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.sel(pwm_clk_mod),
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.clk_out(pwm_clk)
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);
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pwm_core core_R(
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pwm_core core_R(
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.clk(pwm_clk),
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.clk(pwm_clk),
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.rst(rst),
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.rst(rst),
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