generated from maddiebusig/vivado-template-hog
Fix missing PWM clock wire
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8a7ed7a61b
commit
1f1fe1dff0
@ -409,10 +409,13 @@
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wire [3:0] pwm_clk_mod = slv_reg3[11:8];
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wire [3:0] pwm_clk_mod = slv_reg3[11:8];
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wire pwm_oen = slv_reg3[0];
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wire pwm_oen = slv_reg3[0];
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wire pwm_clk;
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wire pwm_clk_en;
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wire pwm_clk_en;
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assign pwm_clk = S_AXI_ACLK;
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clk_enable_pulser clkdiv_pulser (
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clk_enable_pulser clkdiv_pulser (
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.clk(S_AXI_ACLK),
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.clk(pwm_clk),
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.rst(rst),
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.rst(rst),
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.sel(pwm_clk_mod),
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.sel(pwm_clk_mod),
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.en_out(pwm_clk_en)
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.en_out(pwm_clk_en)
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