if { $argc < 4 } {
	error "Usage: vivado -mode batch -source synth.tcl -tclargs DCP PART TOP SRCFILES"
} else {
	puts "All OK"
}

variable DCP [lindex $argv 0]
variable PART [lindex $argv 1]
variable TOP [lindex $argv 2]
variable SRCFILES [lrange ${argv} 3 end]

puts "Synthesizing to DCP $DCP"
puts "Using part $PART"
puts "Using top module $TOP"
puts "Synthesizing sources $SRCFILES"

if {[llength $SRCFILES] == 0} {
	error "No Verilog sources"
}

link_design -part $PART

puts "Reading Verilog sources"
read_verilog $SRCFILES

puts "Synthesizing design"
synth_design -top $TOP -flatten_hierarchy full

puts "Writing Design Checkpoint"
write_checkpoint -force "$DCP"