generated from maddiebusig/vivado-template-hog
26 lines
569 B
Verilog
26 lines
569 B
Verilog
//power-of-2 clock divider
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//output clock frequency can be chosen through the input 'sel'
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//output clock freqeuncy is clk_in/(2^(sel+1))
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module conf_div (
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input clk_in,
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input rst,
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input [3:0] sel,
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output reg clk_out
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);
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wire cl_sel;
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reg [15:0] count;
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assign cl_sel = count[sel];
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always @(posedge clk_in)
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if(rst)
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count<=0;
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else
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count<=count+1;
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always @(posedge clk_in)
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clk_out <= cl_sel;
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endmodule
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