generated from maddiebusig/vivado-template-hog
80 lines
2.1 KiB
Verilog
80 lines
2.1 KiB
Verilog
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`timescale 1 ns / 1 ps
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module rgb_pwm_block #
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(
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// Users to add parameters here
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// User parameters ends
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// Do not modify the parameters beyond this line
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// Parameters of Axi Slave Bus Interface S_AXI
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parameter integer C_S_AXI_DATA_WIDTH = 32,
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parameter integer C_S_AXI_ADDR_WIDTH = 4
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)
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(
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// Users to add ports here
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output wire [2:0] RGB_led,
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// User ports ends
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// Do not modify the ports beyond this line
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// Ports of Axi Slave Bus Interface S_AXI
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input wire s_axi_aclk,
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input wire s_axi_aresetn,
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_axi_awaddr,
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input wire [2 : 0] s_axi_awprot,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [C_S_AXI_DATA_WIDTH-1 : 0] s_axi_wdata,
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input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] s_axi_wstrb,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [1 : 0] s_axi_bresp,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_axi_araddr,
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input wire [2 : 0] s_axi_arprot,
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input wire s_axi_arvalid,
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output wire s_axi_arready,
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output wire [C_S_AXI_DATA_WIDTH-1 : 0] s_axi_rdata,
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output wire [1 : 0] s_axi_rresp,
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output wire s_axi_rvalid,
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input wire s_axi_rready
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);
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// Instantiation of Axi Bus Interface S_AXI
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rgb_pwm_block_S_AXI # (
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.C_S_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
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.C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH)
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) rgb_pwm_block_S_AXI_inst (
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.RGB_led(RGB_led),
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.S_AXI_ACLK(s_axi_aclk),
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.S_AXI_ARESETN(s_axi_aresetn),
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.S_AXI_AWADDR(s_axi_awaddr),
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.S_AXI_AWPROT(s_axi_awprot),
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.S_AXI_AWVALID(s_axi_awvalid),
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.S_AXI_AWREADY(s_axi_awready),
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.S_AXI_WDATA(s_axi_wdata),
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.S_AXI_WSTRB(s_axi_wstrb),
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.S_AXI_WVALID(s_axi_wvalid),
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.S_AXI_WREADY(s_axi_wready),
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.S_AXI_BRESP(s_axi_bresp),
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.S_AXI_BVALID(s_axi_bvalid),
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.S_AXI_BREADY(s_axi_bready),
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.S_AXI_ARADDR(s_axi_araddr),
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.S_AXI_ARPROT(s_axi_arprot),
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.S_AXI_ARVALID(s_axi_arvalid),
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.S_AXI_ARREADY(s_axi_arready),
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.S_AXI_RDATA(s_axi_rdata),
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.S_AXI_RRESP(s_axi_rresp),
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.S_AXI_RVALID(s_axi_rvalid),
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.S_AXI_RREADY(s_axi_rready)
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);
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// Add user logic here
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// User logic ends
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endmodule
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