generated from maddiebusig/vivado-template-hog
73 lines
751 B
Verilog
73 lines
751 B
Verilog
`timescale 1ns/1ps
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module pwm_core_tb #(
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VCD_DUMPFILE = ""
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);
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reg clk = 0;
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reg rst = 1;
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reg [15:0] duty;
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reg [15:0] window_width;
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reg oen = 1;
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wire pulse;
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pwm_core#(
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.WINDOW_REG_SIZE(16)
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) cut (
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.clk(clk),
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.rst(rst),
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.duty(duty),
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.window_width(window_width),
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.oen(oen),
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.pulse(pulse)
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);
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integer k;
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initial begin
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rst = 1;
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clk = 0;
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#10
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rst = 0;
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oen = 1;
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duty = 3;
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window_width = 7;
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for (k=0; k<13; k=k+1) begin
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#5 clk = 1;
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#5 clk = 0;
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end
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duty = 1;
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for (k=0; k<13; k=k+1) begin
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#5 clk = 1;
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#5 clk = 0;
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end
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duty = 1;
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window_width = 2;
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for (k=0; k<8; k=k+1) begin
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#5 clk = 1;
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#5 clk = 0;
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end
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oen = 0;
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for (k=0; k<5; k=k+1) begin
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#5 clk = 1;
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#5 clk = 0;
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end
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$dumpvars;
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$finish;
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end
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endmodule
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