generated from maddiebusig/vivado-template-hog
Madeline Busig
31730fba46
Clock divider implemented in RTL does not get implemented properly when used inside IP block. Instead, this module will pulse an enable pin at the same intervals, which will be used by other modules instead of a separate clock.
59 lines
619 B
Verilog
59 lines
619 B
Verilog
`timescale 1ns/1ps
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module clk_enable_pulser_tb #(
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VCD_DUMPFILE = ""
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);
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reg clk = 0;
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reg rst = 1;
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reg [3:0] sel;
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wire clk_out;
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wire en_out;
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clk_enable_pulser cut (
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.clk(clk),
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.rst(rst),
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.sel(sel),
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.clk_out(clk_out),
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.en_out(en_out)
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);
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reg [4:0] test_counter = 0;
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always @ (posedge clk) begin
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if (en_out) begin
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test_counter <= test_counter + 1;
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end
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end
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integer k;
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initial begin
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rst = 1;
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clk = 0;
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#10
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rst = 0;
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sel = 2;
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for (k=0; k<15; k=k+1) begin
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#5 clk = 1;
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#5 clk = 0;
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end
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sel = 3;
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for (k=0; k<31; k=k+1) begin
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#5 clk = 1;
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#5 clk = 0;
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end
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$dumpvars;
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$finish;
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end
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endmodule
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