`timescale 1ns/1ps

module clk_enable_pulser_tb #(
	VCD_DUMPFILE = ""
);

reg clk = 0;
reg rst = 1;
reg [3:0] sel;

wire clk_out;
wire en_out;

clk_enable_pulser cut (
	.clk(clk),
	.rst(rst),
	.sel(sel),
	.clk_out(clk_out),
	.en_out(en_out)
);

reg [4:0] test_counter = 0;

always @ (posedge clk) begin
	if (en_out) begin
		test_counter <= test_counter + 1;
	end
end

integer k;

initial begin
	rst = 1;
	clk = 0;

	#10

	rst = 0;
	sel = 2;

	for (k=0; k<15; k=k+1) begin
		#5 clk = 1;
		#5 clk = 0;
	end

	sel = 3;

	for (k=0; k<31; k=k+1) begin
		#5 clk = 1;
		#5 clk = 0;
	end

	$dumpvars;
	$finish;
end

endmodule