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base: ee-324:ae5dcf1a4d522c45924d0a25bd3927bec4e83549
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ee-324:trunk
ee-324:v0.0.1
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compare: ee-324:d85f2cf5d8b4021820b2840d876cd1afcdcc0a3e
Branches Tags
ee-324:trunk
ee-324:v0.0.1

5 Commits
ae5dcf1a4d ... d85f2cf5d8

Author SHA1 Message Date
Madeline Busig
d85f2cf5d8 Updtae block design 2025-11-19 16:16:33 -08:00
Madeline Busig
ee6c3d2e60 Fix typos 2025-11-19 16:06:20 -08:00
Madeline Busig
ca29b6c586 Update block diagram, make external 2025-11-19 15:57:04 -08:00
Madeline Busig
72b06dbcb4 Add clock divider functionality to PWM AXI 2025-11-19 15:52:56 -08:00
Madeline Busig
e683fa28c8 Add power of two divider 2025-11-19 15:50:34 -08:00
4 changed files with 174 additions and 22 deletions
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155
BD/pwm_controller/pwm_controller.bd
View File

@ -1,31 +1,97 @@
{
"design": {
"design_info": {
"boundary_crc": "0x0",
"boundary_crc": "0x74C93F5E1FD3DD76",
"device": "xc7z007sclg400-1",
"name": "pwm_controller",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2022.1"
"tool_version": "2022.1",
"validated": "true"
},
"design_tree": {
"processing_system7_0": "",
"rgb_pwm_block_0": "",
"ps7_0_axi_periph": {
"s00_couplers": {}
"s00_couplers": {
"auto_pc": ""
}
},
"rst_ps7_0_50M": ""
"rst_ps7_0_50M": "",
"rgb_pwm_block_0": ""
},
"interface_ports": {
"DDR": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0",
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0"
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
"parameters": {
"AXI_ARBITRATION_SCHEME": {
"value": "TDM",
"value_src": "default"
},
"BURST_LENGTH": {
"value": "8",
"value_src": "default"
},
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"CAS_LATENCY": {
"value": "11",
"value_src": "default"
},
"CAS_WRITE_LATENCY": {
"value": "11",
"value_src": "default"
},
"CS_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_MASK_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_WIDTH": {
"value": "8",
"value_src": "default"
},
"MEMORY_TYPE": {
"value": "COMPONENTS",
"value_src": "default"
},
"MEM_ADDR_MAP": {
"value": "ROW_COLUMN_BANK",
"value_src": "default"
},
"SLOT": {
"value": "Single",
"value_src": "default"
},
"TIMEPERIOD_PS": {
"value": "1250",
"value_src": "default"
}
}
},
"FIXED_IO": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0",
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0"
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
}
}
}
},
"ports": {
"RGB_led_A": {
"direction": "O",
"left": "2",
"right": "0"
}
},
"components": {
@ -932,12 +998,6 @@
}
}
},
"rgb_pwm_block_0": {
"vlnv": "user.org:user:rgb_pwm_block:1.0",
"xci_name": "pwm_controller_rgb_pwm_block_0_0",
"xci_path": "ip/pwm_controller_rgb_pwm_block_0_0/pwm_controller_rgb_pwm_block_0_0.xci",
"inst_hier_path": "rgb_pwm_block_0"
},
"ps7_0_axi_periph": {
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
"xci_path": "ip/pwm_controller_ps7_0_axi_periph_0/pwm_controller_ps7_0_axi_periph_0.xci",
@ -1055,11 +1115,56 @@
"direction": "I"
}
},
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"xci_name": "pwm_controller_auto_pc_0",
"xci_path": "ip/pwm_controller_auto_pc_0/pwm_controller_auto_pc_0.xci",
"inst_hier_path": "ps7_0_axi_periph/s00_couplers/auto_pc",
"parameters": {
"MI_PROTOCOL": {
"value": "AXI4LITE"
},
"SI_PROTOCOL": {
"value": "AXI3"
}
},
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
}
},
"interface_nets": {
"s00_couplers_to_s00_couplers": {
"auto_pc_to_s00_couplers": {
"interface_ports": [
"M_AXI",
"auto_pc/M_AXI"
]
},
"s00_couplers_to_auto_pc": {
"interface_ports": [
"S_AXI",
"M_AXI"
"auto_pc/S_AXI"
]
}
},
"nets": {
"S_ACLK_1": {
"ports": [
"S_ACLK",
"auto_pc/aclk"
]
},
"S_ARESETN_1": {
"ports": [
"S_ARESETN",
"auto_pc/aresetn"
]
}
}
@ -1111,6 +1216,12 @@
"xci_name": "pwm_controller_rst_ps7_0_50M_0",
"xci_path": "ip/pwm_controller_rst_ps7_0_50M_0/pwm_controller_rst_ps7_0_50M_0.xci",
"inst_hier_path": "rst_ps7_0_50M"
},
"rgb_pwm_block_0": {
"vlnv": "user.org:user:rgb_pwm_block:1.0",
"xci_name": "pwm_controller_rgb_pwm_block_0_0",
"xci_path": "ip/pwm_controller_rgb_pwm_block_0_0/pwm_controller_rgb_pwm_block_0_0.xci",
"inst_hier_path": "rgb_pwm_block_0"
}
},
"interface_nets": {
@ -1146,9 +1257,9 @@
"processing_system7_0/M_AXI_GP0_ACLK",
"ps7_0_axi_periph/S00_ACLK",
"rst_ps7_0_50M/slowest_sync_clk",
"rgb_pwm_block_0/s_axi_aclk",
"ps7_0_axi_periph/M00_ACLK",
"ps7_0_axi_periph/ACLK"
"ps7_0_axi_periph/ACLK",
"rgb_pwm_block_0/s_axi_aclk"
]
},
"processing_system7_0_FCLK_RESET0_N": {
@ -1157,13 +1268,19 @@
"rst_ps7_0_50M/ext_reset_in"
]
},
"rgb_pwm_block_0_RGB_led": {
"ports": [
"rgb_pwm_block_0/RGB_led",
"RGB_led_A"
]
},
"rst_ps7_0_50M_peripheral_aresetn": {
"ports": [
"rst_ps7_0_50M/peripheral_aresetn",
"ps7_0_axi_periph/S00_ARESETN",
"rgb_pwm_block_0/s_axi_aresetn",
"ps7_0_axi_periph/M00_ARESETN",
"ps7_0_axi_periph/ARESETN"
"ps7_0_axi_periph/ARESETN",
"rgb_pwm_block_0/s_axi_aresetn"
]
}
},

1
Top/pwm_block/list/pwm_block.src
View File

@ -1,4 +1,5 @@
pwm_block/src/rgb_pwm_block.v top=rgb_pwm_block
pwm_block/src/rgb_pwm_block_S_AXI.v
pwm_block/src/pwm_core.v
pwm_block/src/conf_div.v

25
pwm_block/src/conf_div.v Normal file
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@ -0,0 +1,25 @@
//power-of-2 clock divider
//output clock frequency can be chosen through the input 'sel'
//output clock freqeuncy is clk_in/(2^(sel+1))
module conf_div (
input clk_in,
input rst,
input [3:0] sel,
output reg clk_out
);
wire cl_sel;
reg [15:0] count;
assign cl_sel = count[sel];
always @(posedge clk_in)
if(rst)
count<=0;
else
count<=count+1;
always @(posedge clk_in)
clk_out <= cl_sel;
endmodule

15
pwm_block/src/rgb_pwm_block_S_AXI.v
View File

@ -409,9 +409,18 @@
wire [15:0] duty_G = slv_reg1[15:0];
wire [15:0] duty_B = slv_reg2[15:0];
wire [15:0] widow_width = slv_reg3[31:16];
wire [15:0] pwm_clk_freq = slv_reg3[15:8];
wire [15:0] pwm_oen = slv_reg3[0];
wire [15:0] window_width = slv_reg3[31:16];
wire [3:0] pwm_clk_mod = slv_reg3[11:8];
wire pwm_oen = slv_reg3[0];
wire pwm_clk;
conf_div clk_div (
.clk_in(S_AXI_ACLK),
.rst(S_AXI_ARESETN),
.sel(pwm_clk_mod),
.clk_out(pwm_clk)
);
pwm_core core_R(
.clk(pwm_clk),