Top/hw_pwm_controller/hog.conf

@@ -1,6 +0,0 @@
-#vivado 2022.1
-
-[main]
-PART = xc7z007sclg400-1
-IP_REPO_PATHS = "IP/ UserIP/"
-

Top/hw_pwm_controller/list/hw_pwm_controller.con

@@ -1,2 +0,0 @@
-pwm_controller/con/blackboard.xdc
-

Top/hw_pwm_controller/list/hw_pwm_controller.sim

@@ -1 +0,0 @@
-

Top/hw_pwm_controller/list/hw_pwm_controller.src

@@ -1,4 +0,0 @@
-hw_pwm_controller/src/top.v top=top
-pwm_block/src/pwm_core.v
-pwm_block/src/clk_enable_pulser.v
-

Top/pwm_block/list/clk_enable_pulser_tb.sim

@@ -1,12 +0,0 @@
-# Simulator xsim
-
-[generics]
-VCD_DUMPFILE=clk_enable_pulser_tb.vcd
-
-[properties]
-ACTIVE=1
-TOP=clk_enable_pulser_tb
-
-[files]
-pwm_block/src/clk_enable_pulser.v 
-pwm_block/sim/clk_enable_pulser_tb.v 

Top/pwm_block/list/pwm_block.src

@@ -1,5 +1,5 @@
 pwm_block/src/rgb_pwm_block.v top=rgb_pwm_block
 pwm_block/src/rgb_pwm_block_S_AXI.v
 pwm_block/src/pwm_core.v
-pwm_block/src/clk_enable_pulser.v
+pwm_block/src/conf_div.v
 

hw_pwm_controller/src/top.v

@@ -1,41 +0,0 @@
-`timescale 1ns/1ps
-
-module top (
-	input clk,
-	input [0:0] btn,
-	input [11:0] sw,
-	output [2:0] RGB_led_A,
-	output [7:0] led
-);
-
-wire pulse_en;
-
-clk_enable_pulser enpulser (
-	.clk(clk),
-	.rst(0),
-	.sel(6),
-	.en_out(pulse_en)
-);
-
-wire cur_en = btn[0] ? pulse_en : 1;
-
-wire oen = sw[11];
-assign led[0] = oen;
-
-pwm_core #(
-	.WINDOW_REG_SIZE(8)
-) pwm_core_r (
-	.clk(clk),
-	.en(cur_en),
-	.rst(0),
-	.duty(sw[7:0]),
-	.window_width(255),
-	.oen(oen),
-	.pulse(RGB_led_A[0])
-);
-
-assign RGB_led_A[1] = 0;
-assign RGB_led_A[2] = 0;
-
-endmodule
-

pwm_block/sim/clk_enable_pulser_tb.v

@@ -1,58 +0,0 @@
-`timescale 1ns/1ps
-
-module clk_enable_pulser_tb #(
-	VCD_DUMPFILE = ""
-);
-
-reg clk = 0;
-reg rst = 1;
-reg [3:0] sel;
-
-wire clk_out;
-wire en_out;
-
-clk_enable_pulser cut (
-	.clk(clk),
-	.rst(rst),
-	.sel(sel),
-	.clk_out(clk_out),
-	.en_out(en_out)
-);
-
-reg [4:0] test_counter = 0;
-
-always @ (posedge clk) begin
-	if (en_out) begin
-		test_counter <= test_counter + 1;
-	end
-end
-
-integer k;
-
-initial begin
-	rst = 1;
-	clk = 0;
-
-	#10
-
-	rst = 0;
-	sel = 2;
-
-	for (k=0; k<15; k=k+1) begin
-		#5 clk = 1;
-		#5 clk = 0;
-	end
-
-	sel = 3;
-
-	for (k=0; k<31; k=k+1) begin
-		#5 clk = 1;
-		#5 clk = 0;
-	end
-
-	$dumpvars;
-	$finish;
-end
-
-endmodule
-

pwm_block/sim/pwm_core_tb.v

@@ -5,7 +5,6 @@ module pwm_core_tb #(
 );
 
 reg clk = 0;
-reg en = 1;
 reg rst = 1;
 reg [15:0] duty;
 reg [15:0] window_width;
@@ -17,7 +16,6 @@ pwm_core#(
 	.WINDOW_REG_SIZE(16)
 ) cut (
 	.clk(clk),
-	.en(en)
 	.rst(rst),
 	.duty(duty),
 	.window_width(window_width),

pwm_block/src/clk_enable_pulser.v

@@ -1,19 +0,0 @@
-module clk_enable_pulser (
-	input clk,
-	input rst, 
-	input [3:0] sel,
-	output wire en_out
-);
-
-	reg [15:0] count = 0;
-
-	wire [15:0] trigger_bits = count >> sel;
-
-	always @ (posedge clk) begin
-		if (rst || trigger_bits) count <= 1;
-		else count <= count + 1;
-	end
-
-	assign en_out = count[sel];
-endmodule
-

pwm_block/src/pwm_core.v

@@ -1,10 +1,11 @@
+`timescale 1ns/1ps
+
 /*
 * @brief PWM controller for a single output
 *
 * @param WINDOW_REG_SIZE         Window and duty register size in bits
 *
 * @param [in]  clk           PWM counter clock
-* @param [in]  en            Clock enable
 * @param [in]  rst           Asynchronous reset
 * @param [in]  duty          Duty cycle high time in number of clock cycles
 * @param [in]  window_width  Number of clock cycles in a window 
@@ -15,7 +16,6 @@ module pwm_core #(
 	WINDOW_REG_SIZE = 16
 )(
 	input clk,
-	input en,
 	input rst,
 	input [WINDOW_REG_SIZE-1:0] duty,
 	input [WINDOW_REG_SIZE-1:0] window_width,
@@ -26,13 +26,10 @@ module pwm_core #(
 reg [WINDOW_REG_SIZE-1:0] duty_counter;
 
 always @ (posedge(clk), posedge(rst)) begin
-	if (rst) duty_counter <= 0;
+	if (rst || duty_counter >= window_width - 1)
-	else if (en) begin
+		duty_counter <= 0;
-		if (duty_counter >= window_width - 1)
+	else
-			duty_counter <= 0;
+		duty_counter <= duty_counter + 1;
-		else
-			duty_counter <= duty_counter + 1;
-	end
 end
 
 wire pulse_high;

pwm_block/src/rgb_pwm_block_S_AXI.v

@@ -399,6 +399,10 @@
 	end    
 
 	// Add user logic here
+	wire led_en;
+	assign led_en = slv_reg1[0];
+	assign led = led_en ? slv_reg0[7:0] : 0;
+
 	wire rst = ~S_AXI_ARESETN;
 
 	wire [15:0] duty_R = slv_reg0[15:0];
@@ -409,18 +413,17 @@
 	wire [3:0] pwm_clk_mod = slv_reg3[11:8];
 	wire pwm_oen = slv_reg3[0];
 
-	wire pwm_clk_en;
+	wire pwm_clk;
 
-	clk_enable_pulser clkdiv_pulser (
+	conf_div clk_div (
-		.clk(S_AXI_ACLK),
+		.clk_in(S_AXI_ACLK),
-		.rst(rst),
+		.rst(S_AXI_ARESETN),
 		.sel(pwm_clk_mod),
-		.en_out(pwm_clk_en)
+		.clk_out(pwm_clk)
 	);
 
 	pwm_core core_R(
 		.clk(pwm_clk),
-		.en(pwm_clk_en),
 		.rst(rst),
 		.duty(duty_R),
 		.window_width(window_width),
@@ -430,7 +433,6 @@
 		
 	pwm_core core_G(
 		.clk(pwm_clk),
-		.en(pwm_clk_en),
 		.rst(rst),
 		.duty(duty_G),
 		.window_width(window_width),
@@ -440,7 +442,6 @@
 
 	pwm_core core_B(
 		.clk(pwm_clk),
-		.en(pwm_clk_en),
 		.rst(rst),
 		.duty(duty_B),
 		.window_width(window_width),