Add PWM core testbench sim list

Top/pwm_block/list/pwm_block.src

@@ -1,2 +1,3 @@
 pwm_block/src/top.v top=top
+pwm_block/src/pwm_core.v
 

Top/pwm_block/list/pwm_core_tb.sim

@@ -0,0 +1,12 @@
+# Simulator xsim
+
+[generics]
+VCD_DUMPFILE=pwm_core_tb.vcd
+
+[properties]
+ACTIVE=1
+TOP=pwm_core_tb
+
+[files]
+pwm_block/src/pwm_core.v 
+pwm_block/sim/pwm_core_tb.v 

pwm_block/sim/pwm_core_tb.v

@@ -0,0 +1,72 @@
+`timescale 1ns/1ps
+
+module pwm_core_tb #(
+	VCD_DUMPFILE = ""
+);
+
+reg clk = 0;
+reg rst = 1;
+reg [15:0] duty;
+reg [15:0] window_width;
+reg oen = 1;
+
+wire pulse;
+
+pwm_core#(
+	.WINDOW_REG_SIZE(16)
+) cut (
+	.clk(clk),
+	.rst(rst),
+	.duty(duty),
+	.window_width(window_width),
+	.oen(oen),
+	.pulse(pulse)
+);
+
+integer k;
+
+initial begin
+	rst = 1;
+	clk = 0;
+
+	#10
+
+	rst = 0;
+	oen = 1;
+	duty = 3;
+	window_width = 7;
+
+	for (k=0; k<13; k=k+1) begin
+		#5 clk = 1;
+		#5 clk = 0;
+	end
+
+	duty = 1;
+
+	for (k=0; k<13; k=k+1) begin
+		#5 clk = 1;
+		#5 clk = 0;
+	end
+
+	duty = 1;
+	window_width = 2;
+
+	for (k=0; k<8; k=k+1) begin
+		#5 clk = 1;
+		#5 clk = 0;
+	end
+
+	oen = 0;
+
+	for (k=0; k<5; k=k+1) begin
+		#5 clk = 1;
+		#5 clk = 0;
+	end
+
+
+	$dumpvars;
+	$finish;
+end
+
+endmodule
+

pwm_block/src/pwm_core.v

@@ -25,10 +25,8 @@ module pwm_core #(
 
 reg [WINDOW_REG_SIZE-1:0] duty_counter;
 
-always @ (posedge(clk), rst) begin
+always @ (posedge(clk), posedge(rst)) begin
-	if (rst)
+	if (rst || duty_counter >= window_width - 1)
-		duty_counter <= 0;
-	else if (duty_counter == window_width)
 		duty_counter <= 0;
 	else
 		duty_counter <= duty_counter + 1;