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No commits in common. "53aee5878e184d05815ada057f7ee6d2470d46d0" and "51f3102faea9dd6acca185af6807ada2b700da89" have entirely different histories.

2 changed files with 36 additions and 89 deletions

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@ -16,6 +16,7 @@ ENABLEMENT_DEPENDENCY
INFER=false INFER=false
MODE=slave MODE=slave
PORT.CLK=s_axi_aclk PORT.CLK=s_axi_aclk
PARAMETER.FREQ_HZ=100000000
PARAMETER.ASSOCIATED_RESET=s_axi_aresetn PARAMETER.ASSOCIATED_RESET=s_axi_aresetn
PARAMETER.ASSOCIATED_BUSIF=s_axi PARAMETER.ASSOCIATED_BUSIF=s_axi
@ -24,8 +25,3 @@ INTERFACE=xilinx.com:signal:reset_rtl:1.0
INFER=true INFER=true
PORTS=s_axi_aresetn PORTS=s_axi_aresetn
[memmap.s_axi]
BLOCKS=reg_base
BLOCK.reg_base.BASE_ADDRESS=0
BLOCK.reg_base.RANGE=32

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@ -2,7 +2,7 @@ proc DictValueOr { dict key default } {
if { [dict exists $dict $key] } { if { [dict exists $dict $key] } {
return [dict get $dict $key] return [dict get $dict $key]
} else { } else {
return $default return default
} }
} }
@ -30,48 +30,6 @@ proc SplitSub { str startword } {
} }
} }
# Gets all the values whose key starts with 'startword.*', returns a
# dictionary with the same values, but the keys are instead '*'.
#
# EX: With the dictionary d = { param.foo one param.bar two biz three }
#
# Calling [GetSubValues $d "param"] would result in the dictionary:
#
# { foo one bar two }
proc GetSubValues {map subcat} {
set res_map [dict create]
foreach {key val} $map {
set new_key [SplitSub $key $subcat]
if { $new_key != "" } {
dict append res_map $new_key $val
}
}
return $res_map
}
proc InterfaceAddParameters {iface params} {
foreach {param_name val} $params {
puts "Setting parameter $param_name"
ipx::add_bus_parameter $param_name $iface
set param [ipx::get_bus_parameters $param_name -of_objects $iface]
set_property value $val $param
}
}
proc InterfaceAddPortMaps {iface port_maps} {
foreach {logical_port physical_port} $port_maps {
puts "Mapping logical port $logical_port"
ipx::add_port_map $logical_port $iface
set port_map [ipx::get_port_maps $logical_port -of_objects $iface]
set_property physical_name $physical_port $port_map
}
}
# Parse the interface configuration and create a new interface # Parse the interface configuration and create a new interface
# in the current core # in the current core
# #
@ -135,42 +93,35 @@ proc ParseInterfaceConf { iface_name iface_conf } {
set_property INTERFACE_MODE [dict get $iface_conf "MODE"] $iface set_property INTERFACE_MODE [dict get $iface_conf "MODE"] $iface
} }
set params [GetSubValues $iface_conf "PARAMETER"] # Create user parameters
set port_maps [GetSubValues $iface_conf "PORT"] foreach {key val} $iface_conf {
set param_name [SplitSub $key "PARAMETER"]
InterfaceAddParameters $iface $params if { $param_name == "" } {
InterfaceAddPortMaps $iface $port_maps continue
} }
proc AddMemoryMapBlock {memmap block_name block_conf} { puts "Setting parameter $param_name"
set disp_name [DictValueOr $block_conf "DISPLAY_NAME" ""]
set description [DictValueOr $block_conf "DESCRIPTION" ""]
set base_addr [DictValueOr $block_conf "BASE_ADDRESS" "0"]
set range [DictValueOr $block_conf "RANGE" "4096"]
set width [DictValueOr $block_conf "WIDTH" "0"]
set block [ipx::add_address_block $block_name $memmap] ipx::add_bus_parameter $param_name $iface
set param [ipx::get_bus_parameters $param_name -of_objects $iface]
set_property DISPLAY_NAME $disp_name $block set_property value $val $param
set_property DESCRIPTION $description $block
set_property BASE_ADDRESS $base_addr $block
set_property RANGE $range $block
set_property WIDTH $width $block
} }
proc ParseMemoryMapConf {iface_name memmap_conf} { # Create port mappings
set memmap_name "${iface_name}_mem" foreach {key val} $iface_conf {
set blocks [dict get $memmap_conf "BLOCKS"] set logical_port [SplitSub $key "PORT"]
set physical_port $val
set memmap [ipx::add_memory_map $memmap_name [ipx::current_core]] if { $logical_port == "" } {
set associated_iface [ipx::get_bus_interfaces $iface_name -of_objects [ipx::current_core]] continue
set_property SLAVE_MEMORY_MAP_REF $memmap_name $associated_iface }
foreach block_name $blocks { puts "Mapping logical port $logical_port"
puts "Parsing block $block_name of $memmap_name"
set block_conf [GetSubValues $memmap_conf $block_name] ipx::add_port_map $logical_port $iface
AddMemoryMapBlock $memmap $block_name $block_conf set port_map [ipx::get_port_maps $logical_port -of_objects $iface]
set_property physical_name $physical_port $port_map
} }
} }
@ -249,6 +200,17 @@ foreach memmap [ipx::get_memory_maps -of_objects [ipx::current_core]] {
ipx::remove_memory_map $memmap_name [ipx::current_core] ipx::remove_memory_map $memmap_name [ipx::current_core]
} }
foreach param [ipx::get_user_parameters -of_objects [ipx::current_core]] {
set param_name [lindex $param 2]
if { $param_name == "Component_Name" } {
continue
}
puts "Removing inferred user parameter $param_name"
ipx::remove_user_parameter $param_name [ipx::current_core]
}
puts "Parsing interfaces" puts "Parsing interfaces"
foreach {key val} $ip_conf { foreach {key val} $ip_conf {
@ -262,17 +224,6 @@ foreach {key val} $ip_conf {
} }
} }
puts "Parsing memory maps"
set memmaps [GetSubValues $ip_conf "memmap"]
puts "Memmaps: $memmaps"
foreach {associated_iface memmap_conf} $memmaps {
puts "Parsing memory map for iface $associated_iface, conf: $memmap_conf"
ParseMemoryMapConf $associated_iface $memmap_conf
}
puts "Packaging IP" puts "Packaging IP"
# Increment revision # Increment revision