diff --git a/pwm_block/src/conf_div.v b/pwm_block/src/conf_div.v
new file mode 100644
index 0000000..19990a3
--- /dev/null
+++ b/pwm_block/src/conf_div.v
@@ -0,0 +1,25 @@
+//power-of-2 clock divider
+//output clock frequency can be chosen through the input 'sel'
+//output clock freqeuncy is clk_in/(2^(sel+1))
+module conf_div (
+        input clk_in,
+        input rst,
+        input [3:0] sel,
+        output reg clk_out
+
+);
+        wire cl_sel;
+        reg [15:0] count;
+
+        assign cl_sel = count[sel];
+
+        always @(posedge clk_in)
+                if(rst)
+                        count<=0;
+                else
+                        count<=count+1;
+
+        always @(posedge clk_in)
+                clk_out <= cl_sel;
+endmodule
+