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Updtae block design

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Madeline Busig 2025-11-19 16:16:33 -08:00
parent ee6c3d2e60
commit d85f2cf5d8
1 changed files with 61 additions and 4 deletions
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BD/pwm_controller/pwm_controller.bd
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@ -1,12 +1,13 @@
{
"design": {
"design_info": {
"boundary_crc": "0xCC6CFA539DDF0AAD",
"boundary_crc": "0x74C93F5E1FD3DD76",
"device": "xc7z007sclg400-1",
"name": "pwm_controller",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2022.1"
"tool_version": "2022.1",
"validated": "true"
},
"design_tree": {
"processing_system7_0": "",
@ -22,12 +23,68 @@
"DDR": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0",
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0"
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
"parameters": {
"AXI_ARBITRATION_SCHEME": {
"value": "TDM",
"value_src": "default"
},
"BURST_LENGTH": {
"value": "8",
"value_src": "default"
},
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"CAS_LATENCY": {
"value": "11",
"value_src": "default"
},
"CAS_WRITE_LATENCY": {
"value": "11",
"value_src": "default"
},
"CS_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_MASK_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_WIDTH": {
"value": "8",
"value_src": "default"
},
"MEMORY_TYPE": {
"value": "COMPONENTS",
"value_src": "default"
},
"MEM_ADDR_MAP": {
"value": "ROW_COLUMN_BANK",
"value_src": "default"
},
"SLOT": {
"value": "Single",
"value_src": "default"
},
"TIMEPERIOD_PS": {
"value": "1250",
"value_src": "default"
}
}
},
"FIXED_IO": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0",
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0"
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
}
}
}
},
"ports": {