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Rename memory map name to be more descriptive

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Madeline Busig 2025-11-11 00:08:35 -08:00
parent ca6826d53d
commit cff5b413e7
1 changed files with 5 additions and 0 deletions
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Top/led_controller/ip.conf
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@ -25,3 +25,8 @@ INTERFACE=xilinx.com:signal:reset_rtl:1.0
INFER=true
PORTS=s_axi_aresetn
[memmap.s_axi]
BLOCKS=reg_base
BLOCK.reg_base.BASE_ADDRESS=0
BLOCK.reg_base.RANGE=32