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Update block diagram, make external

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This commit is contained in:
Madeline Busig 2025-11-19 15:57:04 -08:00
parent 72b06dbcb4
commit ca29b6c586
1 changed files with 76 additions and 16 deletions
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92
BD/pwm_controller/pwm_controller.bd
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@ -1,7 +1,7 @@
{
"design": {
"design_info": {
"boundary_crc": "0x0",
"boundary_crc": "0xCC6CFA539DDF0AAD",
"device": "xc7z007sclg400-1",
"name": "pwm_controller",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
@ -10,11 +10,13 @@
},
"design_tree": {
"processing_system7_0": "",
"rgb_pwm_block_0": "",
"ps7_0_axi_periph": {
"s00_couplers": {}
"s00_couplers": {
"auto_pc": ""
}
},
"rst_ps7_0_50M": ""
"rst_ps7_0_50M": "",
"rgb_pwm_block_0": ""
},
"interface_ports": {
"DDR": {
@ -28,6 +30,13 @@
"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0"
}
},
"ports": {
"RGB_led_A": {
"direction": "O",
"left": "2",
"right": "0"
}
},
"components": {
"processing_system7_0": {
"vlnv": "xilinx.com:ip:processing_system7:5.5",
@ -932,12 +941,6 @@
}
}
},
"rgb_pwm_block_0": {
"vlnv": "user.org:user:rgb_pwm_block:1.0",
"xci_name": "pwm_controller_rgb_pwm_block_0_0",
"xci_path": "ip/pwm_controller_rgb_pwm_block_0_0/pwm_controller_rgb_pwm_block_0_0.xci",
"inst_hier_path": "rgb_pwm_block_0"
},
"ps7_0_axi_periph": {
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
"xci_path": "ip/pwm_controller_ps7_0_axi_periph_0/pwm_controller_ps7_0_axi_periph_0.xci",
@ -1055,11 +1058,56 @@
"direction": "I"
}
},
"components": {
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"xci_name": "pwm_controller_auto_pc_0",
"xci_path": "ip/pwm_controller_auto_pc_0/pwm_controller_auto_pc_0.xci",
"inst_hier_path": "ps7_0_axi_periph/s00_couplers/auto_pc",
"parameters": {
"MI_PROTOCOL": {
"value": "AXI4LITE"
},
"SI_PROTOCOL": {
"value": "AXI3"
}
},
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
}
},
"interface_nets": {
"s00_couplers_to_s00_couplers": {
"auto_pc_to_s00_couplers": {
"interface_ports": [
"M_AXI",
"auto_pc/M_AXI"
]
},
"s00_couplers_to_auto_pc": {
"interface_ports": [
"S_AXI",
"M_AXI"
"auto_pc/S_AXI"
]
}
},
"nets": {
"S_ACLK_1": {
"ports": [
"S_ACLK",
"auto_pc/aclk"
]
},
"S_ARESETN_1": {
"ports": [
"S_ARESETN",
"auto_pc/aresetn"
]
}
}
@ -1111,6 +1159,12 @@
"xci_name": "pwm_controller_rst_ps7_0_50M_0",
"xci_path": "ip/pwm_controller_rst_ps7_0_50M_0/pwm_controller_rst_ps7_0_50M_0.xci",
"inst_hier_path": "rst_ps7_0_50M"
},
"rgb_pwm_block_0": {
"vlnv": "user.org:user:rgb_pwm_block:1.0",
"xci_name": "pwm_controller_rgb_pwm_block_0_0",
"xci_path": "ip/pwm_controller_rgb_pwm_block_0_0/pwm_controller_rgb_pwm_block_0_0.xci",
"inst_hier_path": "rgb_pwm_block_0"
}
},
"interface_nets": {
@ -1146,9 +1200,9 @@
"processing_system7_0/M_AXI_GP0_ACLK",
"ps7_0_axi_periph/S00_ACLK",
"rst_ps7_0_50M/slowest_sync_clk",
"rgb_pwm_block_0/s_axi_aclk",
"ps7_0_axi_periph/M00_ACLK",
"ps7_0_axi_periph/ACLK"
"ps7_0_axi_periph/ACLK",
"rgb_pwm_block_0/s_axi_aclk"
]
},
"processing_system7_0_FCLK_RESET0_N": {
@ -1157,13 +1211,19 @@
"rst_ps7_0_50M/ext_reset_in"
]
},
"rgb_pwm_block_0_RGB_led": {
"ports": [
"rgb_pwm_block_0/RGB_led",
"RGB_led_A"
]
},
"rst_ps7_0_50M_peripheral_aresetn": {
"ports": [
"rst_ps7_0_50M/peripheral_aresetn",
"ps7_0_axi_periph/S00_ARESETN",
"rgb_pwm_block_0/s_axi_aresetn",
"ps7_0_axi_periph/M00_ARESETN",
"ps7_0_axi_periph/ARESETN"
"ps7_0_axi_periph/ARESETN",
"rgb_pwm_block_0/s_axi_aresetn"
]
}
},