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Add RGB PWM AXI ip configuration

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Madeline Busig 2025-11-19 15:31:47 -08:00
parent a2c0c9a972
commit a58148a92e
1 changed files with 31 additions and 0 deletions
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Top/pwm_block/ip.conf Normal file
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[main]
ROOT=UserIP/rgb_pwm_block
VENDOR=user.org
LIBRARY=user
# What folder the IP shows up under in Vivado IPI
TAXONOMY=/UserIP
[interface.s_axi]
INTERFACE=xilinx.com:interface:aximm_rtl:1.0
INFER=true
PORTS=s_axi_awaddr s_axi_awprot s_axi_awvalid s_axi_awready s_axi_wdata s_axi_wstrb s_axi_wvalid s_axi_wready s_axi_bresp s_axi_bvalid s_axi_bready s_axi_araddr s_axi_arprot s_axi_arvalid s_axi_arready s_axi_rdata s_axi_rresp s_axi_rvalid s_axi_rready
[interface.s_axi_aclk]
INTERFACE=xilinx.com:signal:clock_rtl:1.0
ENABLEMENT_DEPENDENCY
INFER=false
MODE=slave
PORT.CLK=s_axi_aclk
PARAMETER.ASSOCIATED_RESET=s_axi_aresetn
PARAMETER.ASSOCIATED_BUSIF=s_axi
[interface.s_axi_aresetn]
INTERFACE=xilinx.com:signal:reset_rtl:1.0
INFER=true
PORTS=s_axi_aresetn
[memmap.s_axi]
BLOCKS=reg_base
BLOCK.reg_base.BASE_ADDRESS=0
BLOCK.reg_base.RANGE=32