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Add clock enable input to pwm_core

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This commit is contained in:
Madeline Busig 2025-12-03 00:02:34 -08:00
parent 31730fba46
commit 6b441b12ae
2 changed files with 11 additions and 6 deletions
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2
pwm_block/sim/pwm_core_tb.v
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@ -5,6 +5,7 @@ module pwm_core_tb #(
);
reg clk = 0;
reg en = 1;
reg rst = 1;
reg [15:0] duty;
reg [15:0] window_width;
@ -16,6 +17,7 @@ pwm_core#(
.WINDOW_REG_SIZE(16)
) cut (
.clk(clk),
.en(en)
.rst(rst),
.duty(duty),
.window_width(window_width),

9
pwm_block/src/pwm_core.v
View File

@ -1,11 +1,10 @@
`timescale 1ns/1ps
/*
* @brief PWM controller for a single output
*
* @param WINDOW_REG_SIZE Window and duty register size in bits
*
* @param [in] clk PWM counter clock
* @param [in] en Clock enable
* @param [in] rst Asynchronous reset
* @param [in] duty Duty cycle high time in number of clock cycles
* @param [in] window_width Number of clock cycles in a window
@ -16,6 +15,7 @@ module pwm_core #(
WINDOW_REG_SIZE = 16
)(
input clk,
input en,
input rst,
input [WINDOW_REG_SIZE-1:0] duty,
input [WINDOW_REG_SIZE-1:0] window_width,
@ -26,10 +26,13 @@ module pwm_core #(
reg [WINDOW_REG_SIZE-1:0] duty_counter;
always @ (posedge(clk), posedge(rst)) begin
if (rst || duty_counter >= window_width - 1)
if (rst) duty_counter <= 0;
else if (en) begin
if (duty_counter >= window_width - 1)
duty_counter <= 0;
else
duty_counter <= duty_counter + 1;
end
end
wire pulse_high;