Implement PWM core

pwm_block/src/pwm_core.v

@@ -1,7 +1,43 @@
 `timescale 1ns/1ps
 
-module pwm_core (
+/*
+* @brief PWM controller for a single output
+*
+* @param WINDOW_REG_SIZE         Window and duty register size in bits
+*
+* @param [in]  clk           PWM counter clock
+* @param [in]  rst           Asynchronous reset
+* @param [in]  duty          Duty cycle high time in number of clock cycles
+* @param [in]  window_width  Number of clock cycles in a window 
+* @param [in]  oen           Output pulse enable
+* @param [out] pulse         Output pulse
+*/
+module pwm_core #(
+	WINDOW_REG_SIZE = 16
+)(
+	input clk,
+	input rst,
+	input [WINDOW_REG_SIZE-1:0] duty,
+	input [WINDOW_REG_SIZE-1:0] window_width,
+	input oen,
+	output pulse
 );
 
+reg [WINDOW_REG_SIZE-1:0] duty_counter;
+
+always @ (posedge(clk), rst) begin
+	if (rst)
+		duty_counter <= 0;
+	else if (duty_counter == window_width)
+		duty_counter <= 0;
+	else
+		duty_counter <= duty_counter + 1;
+end
+
+wire pulse_high;
+
+assign pulse_high = (duty_counter < duty) ? 1'b1 : 1'b0;
+assign pulse = oen ? pulse_high : 1'b0;
+
 endmodule