Add clock enable pulser with testbench

Clock divider implemented in RTL does not get implemented properly when
used inside IP block. Instead, this module will pulse an enable pin at
the same intervals, which will be used by other modules instead of a
separate clock.

Top/pwm_block/list/clk_enable_pulser_tb.sim

@@ -0,0 +1,12 @@
+# Simulator xsim
+
+[generics]
+VCD_DUMPFILE=clk_enable_pulser_tb.vcd
+
+[properties]
+ACTIVE=1
+TOP=clk_enable_pulser_tb
+
+[files]
+pwm_block/src/clk_enable_pulser.v 
+pwm_block/sim/clk_enable_pulser_tb.v 

pwm_block/sim/clk_enable_pulser_tb.v

@@ -0,0 +1,58 @@
+`timescale 1ns/1ps
+
+module clk_enable_pulser_tb #(
+	VCD_DUMPFILE = ""
+);
+
+reg clk = 0;
+reg rst = 1;
+reg [3:0] sel;
+
+wire clk_out;
+wire en_out;
+
+clk_enable_pulser cut (
+	.clk(clk),
+	.rst(rst),
+	.sel(sel),
+	.clk_out(clk_out),
+	.en_out(en_out)
+);
+
+reg [4:0] test_counter = 0;
+
+always @ (posedge clk) begin
+	if (en_out) begin
+		test_counter <= test_counter + 1;
+	end
+end
+
+integer k;
+
+initial begin
+	rst = 1;
+	clk = 0;
+
+	#10
+
+	rst = 0;
+	sel = 2;
+
+	for (k=0; k<15; k=k+1) begin
+		#5 clk = 1;
+		#5 clk = 0;
+	end
+
+	sel = 3;
+
+	for (k=0; k<31; k=k+1) begin
+		#5 clk = 1;
+		#5 clk = 0;
+	end
+
+	$dumpvars;
+	$finish;
+end
+
+endmodule
+

pwm_block/src/clk_enable_pulser.v

@@ -0,0 +1,21 @@
+module clk_enable_pulser (
+	input clk,
+	input rst, 
+	input [3:0] sel,
+	output wire clk_out,
+	output wire en_out
+);
+
+	reg [15:0] count = 0;
+
+	wire [15:0] trigger_bits = count >> sel;
+
+	always @ (posedge clk) begin
+		if (rst || trigger_bits) count <= 1;
+		else count <= count + 1;
+	end
+
+	assign clk_out = clk;
+	assign en_out = count[sel];
+endmodule
+