generated from maddiebusig/vivado-template-hog
32 lines
811 B
Verilog
32 lines
811 B
Verilog
`timescale 1ns / 1ps
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module char_rom_tb;
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wire [15:0] DO;
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reg pix_clk = 1'b1;
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reg [10:0] addr = 11'd0;
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// Generate pix_clk
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always
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begin
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#5 pix_clk <= ~pix_clk;
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end
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// Increment Address every clock cycle
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always @ (posedge pix_clk)
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begin
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addr <= addr + 1'b1;
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end
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char_rom char_rom_inst (
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.DO(DO), // Output data, width defined by READ_WIDTH parameter
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.ADDR(addr), // Input address, width defined by read/write port depth
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.CLK(pix_clk), // 1-bit input clock
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.DI(16'h0), // Input data port, width defined by WRITE_WIDTH parameter
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.EN(1'b1), // 1-bit input RAM enable
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.REGCE(1'b0), // 1-bit input output register enable
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.RST(1'b0), // 1-bit input reset
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.WE(2'd0) // Input write enable, width defined by write port depth
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);
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endmodule
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