From bd0430319041eaa9686d6818731a5525f739e106 Mon Sep 17 00:00:00 2001
From: Madeline Busig <madeline.busig@outlook.com>
Date: Wed, 3 Dec 2025 02:56:41 -0800
Subject: [PATCH] Add character rom testbench

---
 Top/vga_character_iface/list/char_rom_tb.sim | 12 ++++++++
 vga_character_iface/sim/char_rom_tb.v        | 31 ++++++++++++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 Top/vga_character_iface/list/char_rom_tb.sim
 create mode 100644 vga_character_iface/sim/char_rom_tb.v

diff --git a/Top/vga_character_iface/list/char_rom_tb.sim b/Top/vga_character_iface/list/char_rom_tb.sim
new file mode 100644
index 0000000..fc37241
--- /dev/null
+++ b/Top/vga_character_iface/list/char_rom_tb.sim
@@ -0,0 +1,12 @@
+# Simulator xsim
+
+# [generics]
+# VCD_DUMPFILE=char_rom_tb.vcd
+
+[properties]
+ACTIVE=1
+TOP=char_rom_tb
+
+[files]
+vga_character_iface/src/char_rom.v 
+vga_character_iface/sim/char_rom_tb.v 
diff --git a/vga_character_iface/sim/char_rom_tb.v b/vga_character_iface/sim/char_rom_tb.v
new file mode 100644
index 0000000..99a65c0
--- /dev/null
+++ b/vga_character_iface/sim/char_rom_tb.v
@@ -0,0 +1,31 @@
+`timescale 1ns / 1ps
+
+module char_rom_tb;
+
+wire [15:0] DO;
+reg pix_clk = 1'b1;
+reg [10:0] addr = 11'd0;
+
+// Generate pix_clk
+always
+begin
+    #5 pix_clk <= ~pix_clk;
+end
+
+// Increment Address every clock cycle
+always @ (posedge pix_clk)
+begin
+    addr <= addr + 1'b1;
+end
+
+char_rom char_rom_inst (
+    .DO(DO),       // Output data, width defined by READ_WIDTH parameter
+    .ADDR(addr),   // Input address, width defined by read/write port depth
+    .CLK(pix_clk),     // 1-bit input clock
+    .DI(16'h0),       // Input data port, width defined by WRITE_WIDTH parameter
+    .EN(1'b1),       // 1-bit input RAM enable
+    .REGCE(1'b0), // 1-bit input output register enable
+    .RST(1'b0),     // 1-bit input reset
+    .WE(2'd0)        // Input write enable, width defined by write port depth
+    );
+endmodule