generated from maddiebusig/vivado-template-hog
Initial commit
This commit is contained in:
ee-324
commit
8973f86cb0
99
.gitignore
vendored
Executable file
99
.gitignore
vendored
Executable file
@ -0,0 +1,99 @@
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# Copyright 2018-2025 The University of Birmingham
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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||||
# You may obtain a copy of the License at
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||||
#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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||||
# Unless required by applicable law or agreed to in writing, software
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||||
# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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### Hog .gitignore ###
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# The following two lines assume that you have your IPs like this: IP/<ip name>/<ip name>.xci
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# If you have a more complex subdirectory structure please make sure that:
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# - the last subdirectory has the same name as the IP and that
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# - only .xci files are committed.
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#
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IP/*/*
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!IP/*/*.xci*
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BD/*
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!BD/*.bd
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## OS
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.DS_Store
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.DS_Store?
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.Trashes
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**.Trashes
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ehthumbs.db
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Thumbs.db
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## MISCELLANEA
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**.tmp
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!/.gitignore
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bin
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gitk
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*~
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**.pyc
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Doc/*
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**.log
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DCPs/
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## CERNbox
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._*
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**._*
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## Sigasi Studio
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.library_mapping.xml
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.project
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.settings
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## Xilinx Vivado
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**.str
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**.jou
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.Xil/
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.Xilinx/
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Projects/
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output/
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lastbuilt.txt
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credentials.sh
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VivadoProject
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SimulationLib
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profpga
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## Intel Quartus Prime
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Projects
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SimulationLib_quartus
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*.bak
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## Software building
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**.depend
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**.layout
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**.o
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bin*/
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obj/
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compile*
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*.out
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## ModelSim, UVVM
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transcript*
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work/
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.cxl*
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# .cxl.modelsim.version # .cxl.ip/
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_*
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_Alert.txt
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_Log.txt
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||||
_info
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||||
**.bak
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||||
**.mti
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||||
**.mtp
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||||
**.mpf
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||||
**.wlf
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||||
**.ini
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||||
**.qdb
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||||
**.qpg
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||||
**.qtl
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||||
3
.gitmodules
vendored
Normal file
3
.gitmodules
vendored
Normal file
@ -0,0 +1,3 @@
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[submodule "Hog"]
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path = Hog
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url = https://gitlab.cern.ch/hog/Hog.git
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1
Hog
Submodule
1
Hog
Submodule
@ -0,0 +1 @@
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Subproject commit 85cce773f8acff6d82dbb9de77bedc8c3ae7b8c6
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9
LICENSE
Normal file
9
LICENSE
Normal file
@ -0,0 +1,9 @@
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MIT License
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||||
|
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Copyright (c) 2025 maddiebusig
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Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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|
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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5
Top/character_display_controller/hog.conf
Normal file
5
Top/character_display_controller/hog.conf
Normal file
@ -0,0 +1,5 @@
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#vivado 2022.1
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[main]
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PART = xc7z007sclg400-1
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@ -0,0 +1,2 @@
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character_display_controller/con/blackboard.xdc
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@ -0,0 +1,2 @@
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character_display_controller/sim/top_tb.v
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character_display_controller/src/top.v top=top
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132
character_display_controller/con/blackboard.xdc
Normal file
132
character_display_controller/con/blackboard.xdc
Normal file
@ -0,0 +1,132 @@
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## Master .xdc for the Blackboard
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##Clock
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set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }];
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#Individual LEDS
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set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L14P_T2_SRCC_34 Schematic=LD0
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set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L14N_T2_SRCC_34 Schematic=LD1
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set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_34 Schematic=LD2
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set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_34 Schematic=LD3
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set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L3P_T0_DWS_PUDC_B_34 Schematic=LD4
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set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_25_34 Schematic=LD5
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set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L16N_T2_34 Schematic=LD6
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set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L17N_T2_34 Schematic=LD7
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set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16P_T2_34 Schematic=LD8
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set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L22N_T3_34 Schematic=LD9
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#RGB_LEDS
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set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_A[0] }]; #IO_L22P_T3_34 Schematic=LD10_R
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set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_A[1] }]; #IO_L18N_T2_34 Schematic=LD10_G
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set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_A[2] }]; #IO_L17P_T2_34 Schematic=LD10_B
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set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_B[0] }]; #IO_L8N_T1_34 Schematic=LD11_R
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set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_B[1] }]; #IO_L7P_T1_34 Schematic=LD11_G
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set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { RGB_led_B[2] }]; #IO_L7N_T1_34 Schematic=LD11_B
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#Switches
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set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_34 Schematic=SW0
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set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L15N_T2_DQS_34 Schematic=SW1
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set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L19P_T3_34 Schematic=SW2
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set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L21N_T3_DQS_AD14N_35 Schematic=SW3
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set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L6N_T0_VREF_34 Schematic=SW4
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set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L6P_T0_34 Schematic=SW5
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set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L22N_T3_AD7N_35 Schematic=SW6
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set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L23N_T3_35 Schematic=SW7
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set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { sw[8] }]; #IO_L10P_T1_34 Sch=VGA_R4_CON
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set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { sw[9] }]; #IO_L10N_T1_34 Sch=VGA_R5_CON
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set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L18P_T2_34 Sch=VGA_R6_CON
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set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R7_CON
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#Push Buttons
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set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L8P_T1_34 Schematic=BTN0
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set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_34 Schematic=BTN1
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set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L24P_T3_34 Schematic=BTN2
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set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L23P_T3_35 Schematic=BTN3
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#Seven Segmen Display Anodes
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set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { seg_an[0] }]; #IO_L10P_T1_AD11P_35 Schematic=SSEG_AN0
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set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { seg_an[1] }]; #IO_L13N_T2_MRCC_35 Schematic=SSEG_AN1
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set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { seg_an[2] }]; #IO_L8N_T1_AD10N_35 Schematic=SSEG_AN2
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set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { seg_an[3] }]; #IO_L11P_T1_SRCC_35 Schematic=SSEG_AN3
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#Seven Segmen Display Cathodes
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set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[0] }]; #IO_L20P_T3_AD6P_35 Schematic=SSEG_CA
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set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[1] }]; #IO_L19P_T3_35 Schematic=SSEG_CB
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set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Schematic=SSEG_CC
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set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[3] }]; #IO_25_35 Schematic=SSEG_CD
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set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[4] }]; #IO_L8P_T1_AD10P_35 Schematic=SSEG_CE
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set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[5] }]; #IO_L24N_T3_AD15N_35 Schematic=SSEG_CF
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set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[6] }]; #IO_L8P_T1_AD10P_35 Schematic=SSEG_CG
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set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { seg_cat[7] }]; #IO_L12N_T1_MRCC_35 Schematic=SSEG_DP
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##Accelerometer/Gyroscope/Magnetometer
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#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { GYRO_SCL }]; #IO_L17N_T2_AD5N_35 Schematic=GYRO_SCL
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#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { GYRO_SDA }]; #IO_L10N_T1_AD11N_35 Schematic=GYRO_SDA
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#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { GYRO_SDO_A/G }]; #IO_L17P_T2_AD5P_35 Schematic=GYRO_SDO_A/G
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#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { GYRO_SDO_M }]; #IO_L11N_T1_SRCC_35 Schematic=GYRO_SDO_M
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#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { GYRO_CS_A/G }]; #IO_L12P_T1_MRCC_35 Schematic=GYRO_CS_A/G
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#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { GYRO_CS_M }]; #IO_L24P_T3_AD15P_35 Schematic=GYRO_CS_M
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#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { DEN_A_G }]; #IO_L20N_T3_AD6N_35 Schematic=GYRO_DEN_A/G
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#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { DRDY_M }]; #IO_L9N_T1_DQS_AD3N_35 Schematic=GYRO_DRDY_M
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#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { INT_A_G }]; #IO_L7N_T1_AD2N_35 Schematic=GYRO_INT_A/G
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#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { INT_M }]; #IO_L9P_T1_DQS_AD3P_35 Schematic=GYRO_INT_M
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||||
|
||||
##MIC
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { M_clk }]; #IO_L21P_T3_DQS_AD14P_35 Schematic=M_CLK
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||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { M_data }]; #IO_L22P_T3_AD7P_35 Schematic=M_DATA
|
||||
|
||||
##Speaker
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { headphone }]; #IO_L16N_T2_35 Schematic=AUDIO
|
||||
|
||||
|
||||
##HDMI Signals
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports hdmi_clk_n]; #IO_L12N_T1_MRCC_34 Sch=HDMI_TX_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports hdmi_clk_p]; #IO_L12P_T1_MRCC_34 Sch=HDMI_TX_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_n[0]]; #IO_L21N_T3_DQS_34 Sch=HDMI_TX0_N
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_p[0]]; #IO_L21P_T3_DQS_34 Sch=HDMI_TX0_P
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_n[1]]; #IO_L23N_T3_34 Sch=HDMI_TX1_N
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_p[1]]; #IO_L23P_T3_34 Sch=HDMI_TX1_P
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_n[2]]; #IO_L13N_T2_MRCC_34 Sch=HDMI_TX2_N
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports hdmi_tx_p[2]]; #IO_L13P_T2_MRCC_34 Sch=HDMI_TX2_P
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L9N_T1_DQS_34 Sch=HDMI_TX_CEC
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L24N_T3_34 Sch=HDMI_TX_HPD
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L20P_T3_34 Sch=HDMI_TX_SCL
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L20N_T3_34 Sch=HDMI_TX_SDA
|
||||
|
||||
##PmodA
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JA1_P }]; #IO_L6P_T0_35 Sch=JA1_P
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { JA1_N }]; #IO_L6N_T0_VREF_35 Sch=JA1_N
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { JA2_P }]; #IO_L18P_T2_AD13P_35 Sch=JA2_P
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { JA2_N }]; #IO_L18N_T2_AD13N_35 Sch=JA2_N
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA3_P }]; #IO_L5P_T0_AD9P_35 Sch=JA3_P
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { JA3_N }]; #IO_L5N_T0_AD9N_35 Sch=JA3_N
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA4_P }]; #IO_L3P_T0_DQS_AD1P_35 Sch=JA4_P
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA4_N }]; #IO_L3N_T0_DQS_AD1N_35 Sch=JA4_N
|
||||
|
||||
##PmodB
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { JB1_P }]; #IO_L4P_T0_35 Sch=JB1_P
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { JB1_N }]; #IO_L4N_T0_35 Sch=JB1_N
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { JB2_P }]; #IO_L15P_T2_DQS_AD12P_35 Sch=JB2_P
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { JB2_N }]; #IO_L15N_T2_DQS_AD12N_35 Sch=JB2_N
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { JB3_P }]; #IO_L1P_T0_AD0P_35 Sch=JB3_P
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { JB3_N }]; #IO_L1N_T0_AD0N_35 Sch=JB3_N
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { JB4_P }]; #IO_L2P_T0_AD8P_35 Sch=JB4_P
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { JB4_N }]; #IO_L2N_T0_AD8N_35 Sch=JB4_N
|
||||
|
||||
##PmodC
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { JC1 }]; #IO_L10P_T1_34 Sch=JC1
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { JC2 }]; #IO_L10N_T1_34 Sch=JC2
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { JC3 }]; #IO_L18P_T2_34 Sch=JC3
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { JC4 }]; #IO_LP9_T1_DQS_34 Sch=JC4
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { JC7 }]; #IO_L7P_T1_AD2P_35 Sch=JC7
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { JC8 }]; #IO_0_35 Sch=JC8
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JC9 }]; #IO_L16P_T2_35 Sch=JC9
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { JC10 }]; #IO_L19N_T3_VREF_35 Sch=JC10
|
||||
|
||||
#Servos
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports servo[0]]; #IO_L16P_T2_35 Sch=SERVO1
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports servo[1]]; #IO_L19N_T3_VREF_35 Sch=SERVO2
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports servo[2]]; #IO_0_35 Sch=SERVO3
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports servo[3]]; #IO_L7P_T1_AD2P_35 Sch=SERVO4
|
||||
6
character_display_controller/sim/top_tb.v
Normal file
6
character_display_controller/sim/top_tb.v
Normal file
@ -0,0 +1,6 @@
|
||||
module top_tv
|
||||
|
||||
finish
|
||||
|
||||
endmodule
|
||||
|
||||
9
character_display_controller/src/top.v
Normal file
9
character_display_controller/src/top.v
Normal file
@ -0,0 +1,9 @@
|
||||
module top(
|
||||
input clk,
|
||||
output [7:0] led
|
||||
);
|
||||
|
||||
assign led = 8'b11111101;
|
||||
|
||||
endmodule
|
||||
|
||||
15
scripts/program_device.sh
Executable file
15
scripts/program_device.sh
Executable file
@ -0,0 +1,15 @@
|
||||
#!/usr/bin/bash
|
||||
|
||||
THISSCRIPT=$(realpath $0)
|
||||
PROJECT_ROOT=$(dirname $(dirname $THISSCRIPT))
|
||||
TCLSCRIPT="$PROJECT_ROOT/tcl/program_device.tcl"
|
||||
|
||||
if [ $# -lt 1 ]; then
|
||||
echo "Usage: $0 BITFILE"
|
||||
exit -1
|
||||
fi
|
||||
|
||||
BITFILE=$1
|
||||
|
||||
$VIVADO_ROOT/bin/vivado -mode batch -source "$TCLSCRIPT" -tclargs "$BITFILE"
|
||||
|
||||
39
tcl/program_device.tcl
Normal file
39
tcl/program_device.tcl
Normal file
@ -0,0 +1,39 @@
|
||||
if { $argc < 1 } {
|
||||
puts "Usage: program_device.sh BITFILE"
|
||||
exit -1
|
||||
}
|
||||
|
||||
set bitfile [lindex $argv 0]
|
||||
|
||||
set hwserver "localhost:3121"
|
||||
set hwtarget "$hwserver/*"
|
||||
|
||||
puts "Opening hardware server at $hwserver"
|
||||
|
||||
open_hw_manager
|
||||
connect_hw_server -url $hwserver
|
||||
|
||||
puts "Opening target $hwtarget"
|
||||
|
||||
set targetlist [get_hw_targets $hwtarget]
|
||||
if { [llength $targetlist] != 1 } {
|
||||
puts "Failed to get hw target. Number of matching targets is not 1."
|
||||
exit -2
|
||||
}
|
||||
|
||||
set target $targetlist
|
||||
|
||||
current_hw_target $target
|
||||
open_hw_target
|
||||
|
||||
puts "Refreshing device"
|
||||
refresh_hw_device [current_hw_device]
|
||||
|
||||
puts "Programming device using bitfile $bitfile"
|
||||
set_property PROGRAM.file "$bitfile" [current_hw_device]
|
||||
program_hw_devices [current_hw_device]
|
||||
refresh_hw_device [current_hw_device]
|
||||
|
||||
puts "Successfully programmed device"
|
||||
exit 0
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user